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The following commit(s) were added to refs/heads/master by this push:
new 350a8b3 arch/stm32: Fix nxstyle errors
350a8b3 is described below
commit 350a8b31a8e08206c65285d4eb94b3b3672bc9ac
Author: Nathan Hartman <59230071+hartmannat...@users.noreply.github.com>
AuthorDate: Tue Dec 1 17:11:28 2020 -0500
arch/stm32: Fix nxstyle errors
arch/arm/src/stm32/hardware/stm32_adc.h:
* Fix nxstyle errors.
arch/arm/src/stm32/hardware/stm32_adc_v2.h:
* Fix nxstyle errors.
---
arch/arm/src/stm32/hardware/stm32_adc.h | 11 ++++----
arch/arm/src/stm32/hardware/stm32_adc_v2.h | 42 ++++++++++++++++--------------
2 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/arch/arm/src/stm32/hardware/stm32_adc.h
b/arch/arm/src/stm32/hardware/stm32_adc.h
index 4622ab5..9217a91 100644
--- a/arch/arm/src/stm32/hardware/stm32_adc.h
+++ b/arch/arm/src/stm32/hardware/stm32_adc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************************
+/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_adc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -31,14 +31,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
-
****************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H
-/****************************************************************************************************
+/****************************************************************************
* Included Files
-
****************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
@@ -56,7 +56,8 @@
* which differs too much to keep it in the same file as ADC IPv1.
*/
-#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) &&
defined(CONFIG_STM32_HAVE_IP_ADC_V2)
+#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && \
+ defined(CONFIG_STM32_HAVE_IP_ADC_V2)
# error Only one STM32 ADC IP version must be selected
#endif
diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h
b/arch/arm/src/stm32/hardware/stm32_adc_v2.h
index e625435..5b52c8a 100644
--- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h
+++ b/arch/arm/src/stm32/hardware/stm32_adc_v2.h
@@ -1,4 +1,4 @@
-/****************************************************************************************************
+/****************************************************************************
* arch/arm/src/stm32/hardware/stm32_adc_v2.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -32,26 +32,28 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
-
****************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H
-/****************************************************************************************************
+/****************************************************************************
* Included Files
-
****************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
-/****************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
-
****************************************************************************************************/
+ ****************************************************************************/
-/* Configuration
************************************************************************************/
+/* Configuration ************************************************************/
-/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), G4, H7,
L0, L4, L4+ */
+/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), G4,
+ * H7, L0, L4, L4+
+ */
#define HAVE_IP_ADC_V2
#undef HAVE_IP_ADC_V1 /* No ADC IPv1 */
@@ -84,7 +86,7 @@
# define HAVE_ADC_CFGR2
#endif
-/* Base addresses
***********************************************************************************/
+/* Base addresses ***********************************************************/
#define STM32_ADC1_OFFSET 0x0000
#define STM32_ADC2_OFFSET 0x0100
@@ -99,7 +101,7 @@
#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET +
STM32_ADC12_BASE) /* ADC1, ADC2 common */
#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET +
STM32_ADC34_BASE) /* ADC3, ADC4 common */
-/* Register Offsets
*********************************************************************************/
+/* Register Offsets *********************************************************/
#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status
register */
#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable
register */
@@ -138,7 +140,7 @@
#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */
#define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register
for dual mode */
-/* Register Addresses
*******************************************************************************/
+/* Register Addresses *******************************************************/
#if STM32_NADC > 0
# define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET)
@@ -284,9 +286,11 @@
# define STM32_ADC34_CDR (STM32_ADC34CMN_BASE +
STM32_ADC_CDR_OFFSET)
#endif
-/* Register Bitfield Definitions
********************************************************************/
+/* Register Bitfield Definitions ********************************************/
-/* ADC interrupt and status register (ISR) and ADC interrupt enable register
(IER) */
+/* ADC interrupt and status register (ISR), and
+ * ADC interrupt enable register (IER)
+ */
#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */
#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling
flag */
@@ -860,16 +864,16 @@
#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data
of the slave ADC */
#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT)
-/****************************************************************************************************
+/****************************************************************************
* Public Types
-
****************************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************************
+/****************************************************************************
* Public Data
-
****************************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************************
+/****************************************************************************
* Public Function Prototypes
-
****************************************************************************************************/
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H */
