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commit 8b212ae040c0961493d6633f219cdb2ae22343f1
Author: YAMAMOTO Takashi <yamam...@midokura.com>
AuthorDate: Thu Nov 26 12:20:54 2020 +0900
arch/arm/src/stm32/stm32_i2c_alt.c: Fix syslog formats
---
arch/arm/src/stm32/stm32_i2c_alt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c
b/arch/arm/src/stm32/stm32_i2c_alt.c
index 3627833..8eccf65 100644
--- a/arch/arm/src/stm32/stm32_i2c_alt.c
+++ b/arch/arm/src/stm32/stm32_i2c_alt.c
@@ -1413,7 +1413,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s
*priv)
else if ((status & I2C_SR1_ADDR) == 0 && priv->check_addr_ack)
{
i2cinfo("Invalid Address. Setting stop bit and clearing message\n");
- i2cinfo("status %i\n", status);
+ i2cinfo("status %" PRIi32 "\n", status);
/* Set condition to terminate msg chain transmission as address is
invalid. */
@@ -1821,7 +1821,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s
*priv)
status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16);
i2cerr("ERROR: No correct state detected(start bit, read or write) \n");
- i2cerr(" state %i\n", status);
+ i2cerr(" state %" PRIi32 "\n", status);
/* Set condition to terminate ISR and wake waiting thread */
