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commit 65e3f68af821b4b54e4a9262c373fc84d22222e0 Author: raiden00pl <[email protected]> AuthorDate: Tue Jun 9 14:46:55 2026 +0200 !arch/stm32u5: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32U5 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl <[email protected]> --- arch/arm/src/stm32u5/hardware/stm32_memorymap.h | 4 +- arch/arm/src/stm32u5/hardware/stm32_tim.h | 508 ++++++++++----------- arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h | 44 +- arch/arm/src/stm32u5/stm32_rcc.c | 16 +- arch/arm/src/stm32u5/stm32_tim.c | 332 +++++++------- arch/arm/src/stm32u5/stm32_tim.h | 72 +-- arch/arm/src/stm32u5/stm32_tim_lowerhalf.c | 82 ++-- arch/arm/src/stm32u5/stm32_uid.c | 6 +- .../stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c | 2 +- 9 files changed, 533 insertions(+), 533 deletions(-) diff --git a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h index 616cb5e855e..90fe085d6ee 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h @@ -40,8 +40,8 @@ #define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ #define STM32_REGION_MASK 0xF0000000 -#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_SRAM_BASE) -#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_FMC_BANK1) +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) /* Code Base Addresses ******************************************************/ diff --git a/arch/arm/src/stm32u5/hardware/stm32_tim.h b/arch/arm/src/stm32u5/hardware/stm32_tim.h index d9adc748102..e180a60d773 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32u5/hardware/stm32_tim.h @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32U5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32U5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32U5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32U5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32U5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32U5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32U5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32U5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32U5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32U5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32U5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32U5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32U5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32U5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32U5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32U5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32U5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32U5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32U5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32U5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32U5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32U5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32U5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32U5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32U5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32U5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32U5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32U5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32U5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32U5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32U5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32U5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32U5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32U5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32U5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32U5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32U5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32U5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32U5_TIM1_CR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CR1_OFFSET) -#define STM32U5_TIM1_CR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CR2_OFFSET) -#define STM32U5_TIM1_SMCR (STM32U5_TIM1_BASE + STM32U5_ATIM_SMCR_OFFSET) -#define STM32U5_TIM1_DIER (STM32U5_TIM1_BASE + STM32U5_ATIM_DIER_OFFSET) -#define STM32U5_TIM1_SR (STM32U5_TIM1_BASE + STM32U5_ATIM_SR_OFFSET) -#define STM32U5_TIM1_EGR (STM32U5_TIM1_BASE + STM32U5_ATIM_EGR_OFFSET) -#define STM32U5_TIM1_CCMR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR1_OFFSET) -#define STM32U5_TIM1_CCMR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR2_OFFSET) -#define STM32U5_TIM1_CCER (STM32U5_TIM1_BASE + STM32U5_ATIM_CCER_OFFSET) -#define STM32U5_TIM1_CNT (STM32U5_TIM1_BASE + STM32U5_ATIM_CNT_OFFSET) -#define STM32U5_TIM1_PSC (STM32U5_TIM1_BASE + STM32U5_ATIM_PSC_OFFSET) -#define STM32U5_TIM1_ARR (STM32U5_TIM1_BASE + STM32U5_ATIM_ARR_OFFSET) -#define STM32U5_TIM1_RCR (STM32U5_TIM1_BASE + STM32U5_ATIM_RCR_OFFSET) -#define STM32U5_TIM1_CCR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR1_OFFSET) -#define STM32U5_TIM1_CCR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR2_OFFSET) -#define STM32U5_TIM1_CCR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR3_OFFSET) -#define STM32U5_TIM1_CCR4 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR4_OFFSET) -#define STM32U5_TIM1_BDTR (STM32U5_TIM1_BASE + STM32U5_ATIM_BDTR_OFFSET) -#define STM32U5_TIM1_DCR (STM32U5_TIM1_BASE + STM32U5_ATIM_DCR_OFFSET) -#define STM32U5_TIM1_DMAR (STM32U5_TIM1_BASE + STM32U5_ATIM_DMAR_OFFSET) -#define STM32U5_TIM1_OR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR1_OFFSET) -#define STM32U5_TIM1_CCMR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR3_OFFSET) -#define STM32U5_TIM1_CCR5 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR5_OFFSET) -#define STM32U5_TIM1_CCR6 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR6_OFFSET) -#define STM32U5_TIM1_OR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR2_OFFSET) -#define STM32U5_TIM1_OR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR3_OFFSET) - -#define STM32U5_TIM8_CR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CR1_OFFSET) -#define STM32U5_TIM8_CR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CR2_OFFSET) -#define STM32U5_TIM8_SMCR (STM32U5_TIM8_BASE + STM32U5_ATIM_SMCR_OFFSET) -#define STM32U5_TIM8_DIER (STM32U5_TIM8_BASE + STM32U5_ATIM_DIER_OFFSET) -#define STM32U5_TIM8_SR (STM32U5_TIM8_BASE + STM32U5_ATIM_SR_OFFSET) -#define STM32U5_TIM8_EGR (STM32U5_TIM8_BASE + STM32U5_ATIM_EGR_OFFSET) -#define STM32U5_TIM8_CCMR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR1_OFFSET) -#define STM32U5_TIM8_CCMR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR2_OFFSET) -#define STM32U5_TIM8_CCER (STM32U5_TIM8_BASE + STM32U5_ATIM_CCER_OFFSET) -#define STM32U5_TIM8_CNT (STM32U5_TIM8_BASE + STM32U5_ATIM_CNT_OFFSET) -#define STM32U5_TIM8_PSC (STM32U5_TIM8_BASE + STM32U5_ATIM_PSC_OFFSET) -#define STM32U5_TIM8_ARR (STM32U5_TIM8_BASE + STM32U5_ATIM_ARR_OFFSET) -#define STM32U5_TIM8_RCR (STM32U5_TIM8_BASE + STM32U5_ATIM_RCR_OFFSET) -#define STM32U5_TIM8_CCR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR1_OFFSET) -#define STM32U5_TIM8_CCR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR2_OFFSET) -#define STM32U5_TIM8_CCR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR3_OFFSET) -#define STM32U5_TIM8_CCR4 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR4_OFFSET) -#define STM32U5_TIM8_BDTR (STM32U5_TIM8_BASE + STM32U5_ATIM_BDTR_OFFSET) -#define STM32U5_TIM8_DCR (STM32U5_TIM8_BASE + STM32U5_ATIM_DCR_OFFSET) -#define STM32U5_TIM8_DMAR (STM32U5_TIM8_BASE + STM32U5_ATIM_DMAR_OFFSET) -#define STM32U5_TIM8_OR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR1_OFFSET) -#define STM32U5_TIM8_CCMR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR3_OFFSET) -#define STM32U5_TIM8_CCR5 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR5_OFFSET) -#define STM32U5_TIM8_CCR6 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR6_OFFSET) -#define STM32U5_TIM8_OR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR2_OFFSET) -#define STM32U5_TIM8_OR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE + STM32_ATIM_OR3_OFFSET) + +#define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE + STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32U5_TIM2_CR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM2_CR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM2_SMCR (STM32U5_TIM2_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM2_DIER (STM32U5_TIM2_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM2_SR (STM32U5_TIM2_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM2_EGR (STM32U5_TIM2_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM2_CCMR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM2_CCMR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM2_CCER (STM32U5_TIM2_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM2_CNT (STM32U5_TIM2_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM2_PSC (STM32U5_TIM2_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM2_ARR (STM32U5_TIM2_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM2_CCR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM2_CCR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM2_CCR3 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM2_CCR4 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM2_DCR (STM32U5_TIM2_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM2_DMAR (STM32U5_TIM2_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM2_OR (STM32U5_TIM2_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM3_CR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM3_CR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM3_SMCR (STM32U5_TIM3_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM3_DIER (STM32U5_TIM3_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM3_SR (STM32U5_TIM3_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM3_EGR (STM32U5_TIM3_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM3_CCMR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM3_CCMR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM3_CCER (STM32U5_TIM3_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM3_CNT (STM32U5_TIM3_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM3_PSC (STM32U5_TIM3_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM3_ARR (STM32U5_TIM3_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM3_CCR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM3_CCR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM3_CCR3 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM3_CCR4 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM3_DCR (STM32U5_TIM3_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM3_DMAR (STM32U5_TIM3_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM4_CR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM4_CR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM4_SMCR (STM32U5_TIM4_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM4_DIER (STM32U5_TIM4_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM4_SR (STM32U5_TIM4_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM4_EGR (STM32U5_TIM4_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM4_CCMR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM4_CCMR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM4_CCER (STM32U5_TIM4_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM4_CNT (STM32U5_TIM4_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM4_PSC (STM32U5_TIM4_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM4_ARR (STM32U5_TIM4_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM4_CCR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM4_CCR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM4_CCR3 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM4_CCR4 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM4_DCR (STM32U5_TIM4_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM4_DMAR (STM32U5_TIM4_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM5_CR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM5_CR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM5_SMCR (STM32U5_TIM5_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM5_DIER (STM32U5_TIM5_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM5_SR (STM32U5_TIM5_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM5_EGR (STM32U5_TIM5_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM5_CCMR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM5_CCMR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM5_CCER (STM32U5_TIM5_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM5_CNT (STM32U5_TIM5_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM5_PSC (STM32U5_TIM5_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM5_ARR (STM32U5_TIM5_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM5_CCR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM5_CCR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM5_CCR3 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM5_CCR4 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM5_DCR (STM32U5_TIM5_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM5_DMAR (STM32U5_TIM5_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM5_OR (STM32U5_TIM5_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM15_CR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM15_CR2 (STM32U5_TIM15_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM15_SMCR (STM32U5_TIM15_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM15_DIER (STM32U5_TIM15_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM15_SR (STM32U5_TIM15_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM15_EGR (STM32U5_TIM15_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM15_CCMR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM15_CCER (STM32U5_TIM15_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM15_CNT (STM32U5_TIM15_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM15_PSC (STM32U5_TIM15_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM15_ARR (STM32U5_TIM15_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM15_RCR (STM32U5_TIM15_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM15_CCR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM15_CCR2 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM15_BDTR (STM32U5_TIM15_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM15_DCR (STM32U5_TIM15_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM15_DMAR (STM32U5_TIM15_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM16_CR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM16_CR2 (STM32U5_TIM16_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM16_DIER (STM32U5_TIM16_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM16_SR (STM32U5_TIM16_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM16_EGR (STM32U5_TIM16_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM16_CCMR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM16_CCER (STM32U5_TIM16_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM16_CNT (STM32U5_TIM16_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM16_PSC (STM32U5_TIM16_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM16_ARR (STM32U5_TIM16_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM16_RCR (STM32U5_TIM16_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM16_CCR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM16_BDTR (STM32U5_TIM16_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM16_DCR (STM32U5_TIM16_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM16_DMAR (STM32U5_TIM16_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM16_OR (STM32U5_TIM16_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM17_CR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM17_CR2 (STM32U5_TIM17_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM17_DIER (STM32U5_TIM17_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM17_SR (STM32U5_TIM17_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM17_EGR (STM32U5_TIM17_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM17_CCMR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM17_CCER (STM32U5_TIM17_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM17_CNT (STM32U5_TIM17_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM17_PSC (STM32U5_TIM17_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM17_ARR (STM32U5_TIM17_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM17_RCR (STM32U5_TIM17_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM17_CCR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM17_BDTR (STM32U5_TIM17_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM17_DCR (STM32U5_TIM17_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM17_DMAR (STM32U5_TIM17_BASE + STM32U5_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32U5_TIM6_CR1 (STM32U5_TIM6_BASE + STM32U5_BTIM_CR1_OFFSET) -#define STM32U5_TIM6_CR2 (STM32U5_TIM6_BASE + STM32U5_BTIM_CR2_OFFSET) -#define STM32U5_TIM6_DIER (STM32U5_TIM6_BASE + STM32U5_BTIM_DIER_OFFSET) -#define STM32U5_TIM6_SR (STM32U5_TIM6_BASE + STM32U5_BTIM_SR_OFFSET) -#define STM32U5_TIM6_EGR (STM32U5_TIM6_BASE + STM32U5_BTIM_EGR_OFFSET) -#define STM32U5_TIM6_CNT (STM32U5_TIM6_BASE + STM32U5_BTIM_CNT_OFFSET) -#define STM32U5_TIM6_PSC (STM32U5_TIM6_BASE + STM32U5_BTIM_PSC_OFFSET) -#define STM32U5_TIM6_ARR (STM32U5_TIM6_BASE + STM32U5_BTIM_ARR_OFFSET) - -#define STM32U5_TIM7_CR1 (STM32U5_TIM7_BASE + STM32U5_BTIM_CR1_OFFSET) -#define STM32U5_TIM7_CR2 (STM32U5_TIM7_BASE + STM32U5_BTIM_CR2_OFFSET) -#define STM32U5_TIM7_DIER (STM32U5_TIM7_BASE + STM32U5_BTIM_DIER_OFFSET) -#define STM32U5_TIM7_SR (STM32U5_TIM7_BASE + STM32U5_BTIM_SR_OFFSET) -#define STM32U5_TIM7_EGR (STM32U5_TIM7_BASE + STM32U5_BTIM_EGR_OFFSET) -#define STM32U5_TIM7_CNT (STM32U5_TIM7_BASE + STM32U5_BTIM_CNT_OFFSET) -#define STM32U5_TIM7_PSC (STM32U5_TIM7_BASE + STM32U5_BTIM_PSC_OFFSET) -#define STM32U5_TIM7_ARR (STM32U5_TIM7_BASE + STM32U5_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index 56fc25f0624..20bb8da6654 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -41,31 +41,31 @@ /* Register Offsets *********************************************************/ -#define STM32U5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32U5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32U5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32U5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32U5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32U5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32U5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32U5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32U5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32U5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32U5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32U5_SYSCFG_SECCFGR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SECCFGR_OFFSET) -#define STM32U5_SYSCFG_CFGR1 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR1_OFFSET) -#define STM32U5_SYSCFG_FPUIMR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_FPUIMR_OFFSET) -#define STM32U5_SYSCFG_CNSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CNSLCKR_OFFSET) -#define STM32U5_SYSCFG_CSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CSLCKR_OFFSET) -#define STM32U5_SYSCFG_CFGR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR2_OFFSET) -#define STM32U5_SYSCFG_SCSR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SCSR_OFFSET) -#define STM32U5_SYSCFG_SKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SKR_OFFSET) -#define STM32U5_SYSCFG_SWPR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR_OFFSET) -#define STM32U5_SYSCFG_SWPR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR2_OFFSET) -#define STM32U5_SYSCFG_RSSCMDR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_RSSCMDR_OFFSET) +#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) +#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) +#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32u5/stm32_rcc.c b/arch/arm/src/stm32u5/stm32_rcc.c index aa334d99305..2b2972cde72 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.c +++ b/arch/arm/src/stm32u5/stm32_rcc.c @@ -93,14 +93,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32U5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32U5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32U5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -113,19 +113,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32U5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32U5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32U5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32U5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32U5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32_pwr_enablebkp(false); diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c index 5e15c461d18..7dbdba50ce4 100644 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ b/arch/arm/src/stm32u5/stm32_tim.c @@ -305,16 +305,16 @@ static const struct stm32_tim_ops_s stm32_tim_ops = struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32U5_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -322,8 +322,8 @@ struct stm32_tim_priv_s stm32_tim2_priv = struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif @@ -331,8 +331,8 @@ struct stm32_tim_priv_s stm32_tim3_priv = struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif @@ -340,8 +340,8 @@ struct stm32_tim_priv_s stm32_tim4_priv = struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif @@ -349,8 +349,8 @@ struct stm32_tim_priv_s stm32_tim5_priv = struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif @@ -358,8 +358,8 @@ struct stm32_tim_priv_s stm32_tim6_priv = struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif @@ -367,8 +367,8 @@ struct stm32_tim_priv_s stm32_tim7_priv = struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif @@ -376,8 +376,8 @@ struct stm32_tim_priv_s stm32_tim8_priv = struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif @@ -385,8 +385,8 @@ struct stm32_tim_priv_s stm32_tim15_priv = struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -394,8 +394,8 @@ struct stm32_tim_priv_s stm32_tim16_priv = struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -483,9 +483,9 @@ static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32U5_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -494,10 +494,10 @@ static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -506,9 +506,9 @@ static void stm32_tim_enable(struct stm32_tim_dev_s *dev) static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -522,7 +522,7 @@ static void stm32_tim_disable(struct stm32_tim_dev_s *dev) static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_DISABLED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32_tim_disable(dev); } @@ -540,7 +540,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32U5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32_configgpio(cfg); } @@ -566,13 +566,13 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32U5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32U5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32U5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32U5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32U5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, break; - case STM32U5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,15 +611,15 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32U5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32_modifyreg16(dev, STM32U5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -655,66 +655,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,7 +745,7 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, prescaler = 0xffff; } - stm32_putreg16(dev, STM32U5_GTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -770,64 +770,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,7 +837,7 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32_getreg16(dev, STM32U5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -849,7 +849,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32U5_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -859,7 +859,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32U5_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -869,7 +869,7 @@ static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32U5_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -879,10 +879,10 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: #endif return counter; @@ -906,7 +906,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32U5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32_getreg16(dev, STM32U5_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32U5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32U5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32U5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32U5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,21 +974,21 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32U5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32U5_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1021,7 +1021,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1054,7 +1054,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1087,7 +1087,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1119,7 +1119,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1152,7 +1152,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1185,7 +1185,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1218,7 +1218,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1251,7 +1251,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1303,19 +1303,19 @@ static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - stm32_putreg32(dev, STM32U5_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32_putreg32(dev, STM32U5_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32_putreg32(dev, STM32U5_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32_putreg32(dev, STM32U5_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1337,16 +1337,16 @@ static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - return stm32_getreg32(dev, STM32U5_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32_getreg32(dev, STM32U5_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32_getreg32(dev, STM32U5_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32_getreg32(dev, STM32U5_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1367,66 +1367,66 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: - vectorno = STM32U5_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: - vectorno = STM32U5_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: - vectorno = STM32U5_IRQ_TIM3; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: - vectorno = STM32U5_IRQ_TIM4; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: - vectorno = STM32U5_IRQ_TIM5; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: - vectorno = STM32U5_IRQ_TIM6; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: - vectorno = STM32U5_IRQ_TIM7; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: - vectorno = STM32U5_IRQ_TIM8UP; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: - vectorno = STM32U5_IRQ_TIM15; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: - vectorno = STM32U5_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: - vectorno = STM32U5_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1459,7 +1459,7 @@ static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1470,7 +1470,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1479,7 +1479,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32_putreg16(dev, STM32U5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1489,7 +1489,7 @@ static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32_getreg16(dev, STM32U5_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1512,76 +1512,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) #ifdef CONFIG_STM32U5_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32U5_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32U5_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32U5_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32U5_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32U5_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32U5_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32U5_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32U5_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32U5_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32U5_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,7 +1591,7 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32_tim_priv_s *)dev)->mode != STM32U5_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1617,67 +1617,67 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,7 +1687,7 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32u5/stm32_tim.h b/arch/arm/src/stm32u5/stm32_tim.h index e043e98f0e0..f61751552dd 100644 --- a/arch/arm/src/stm32u5/stm32_tim.h +++ b/arch/arm/src/stm32u5/stm32_tim.h @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32U5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32U5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32U5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32U5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32U5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32U5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32U5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32U5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32U5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32U5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32U5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32U5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32U5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32U5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32_tim_dev_s enum stm32_tim_mode_e { - STM32U5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32U5_TIM_MODE_MASK = 0x0310, - STM32U5_TIM_MODE_DISABLED = 0x0000, - STM32U5_TIM_MODE_UP = 0x0100, - STM32U5_TIM_MODE_DOWN = 0x0110, - STM32U5_TIM_MODE_UPDOWN = 0x0200, - STM32U5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32U5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32U5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32U5_TIM_MODE_CK_EXT = 0x0800, - STM32U5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32U5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32U5_TIM_MODE_CK_CH1 = 0x0001, - STM32U5_TIM_MODE_CK_CH2 = 0x0002, - STM32U5_TIM_MODE_CK_CH3 = 0x0003, - STM32U5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,22 +118,22 @@ enum stm32_tim_mode_e enum stm32_tim_channel_e { - STM32U5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32U5_TIM_CH_POLARITY_POS = 0x00, - STM32U5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32U5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32U5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32U5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ diff --git a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c index 92e5739a233..7752a4fda1b 100644 --- a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c @@ -52,17 +52,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32U5_TIM1_RES 16 -#define STM32U5_TIM2_RES 32 -#define STM32U5_TIM3_RES 16 -#define STM32U5_TIM4_RES 16 -#define STM32U5_TIM5_RES 32 -#define STM32U5_TIM6_RES 16 -#define STM32U5_TIM7_RES 16 -#define STM32U5_TIM8_RES 16 -#define STM32U5_TIM15_RES 16 -#define STM32U5_TIM16_RES 16 -#define STM32U5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -122,7 +122,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -130,7 +130,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -138,7 +138,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif @@ -146,7 +146,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif @@ -154,7 +154,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif @@ -162,7 +162,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif @@ -170,7 +170,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif @@ -178,7 +178,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif @@ -186,7 +186,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif @@ -194,7 +194,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -202,7 +202,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32_timer_handler(int irq, void *context, void *arg) (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32U5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32U5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32U5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_DISABLED); - STM32U5_TIM_DISABLEINT(priv->tim, 0); - STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32U5_TIM_GETCLOCK(priv->tim); - period = STM32U5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32U5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32U5_TIM_SETCLOCK(priv->tim, freq); - STM32U5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32U5_TIM_SETCLOCK(priv->tim, 1000000); - STM32U5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32U5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32U5_TIM_DISABLEINT(priv->tim, 0); - STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32u5/stm32_uid.c b/arch/arm/src/stm32u5/stm32_uid.c index 55b3aa8e82a..479826dafd2 100644 --- a/arch/arm/src/stm32u5/stm32_uid.c +++ b/arch/arm/src/stm32u5/stm32_uid.c @@ -29,7 +29,7 @@ #include "hardware/stm32_memorymap.h" #include "stm32_uid.h" -#ifdef STM32U5_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -41,8 +41,8 @@ void stm32_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32U5_SYSMEM_UID) + i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); } } -#endif /* STM32U5_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c index 2d246c3377f..5cde87263ab 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c @@ -118,7 +118,7 @@ int stm32_bringup(void) return -1; } -#if defined(STM32U5_I2C2) +#if defined(STM32_I2C2) i2c2_m = stm32_i2cbus_initialize(2); if (i2c2_m == NULL) {
