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commit a82293e3efba51341444b217e3dc8134a06175e6 Author: Maarten Zanders <[email protected]> AuthorDate: Tue Feb 24 10:43:32 2026 +0100 arch/arm/imx9: make MU driver generic for all i.MX9 variants. Rename imx95_mu_* functions to imx9_mu_*, decoupling the MU driver API from the iMX95-specific naming in preparation for iMX93-M33 support. Add ARCH_CHIP_IMX95_M7 dependency to the MU instance Kconfig entries so they are only visible for the appropriate target. Switch imx9_mu.c to include the generic imx9_memorymap.h instead of the imx95-specific header. Fix incorrect help text for MU8 (was copy-pasted from MU5). Signed-off-by: Maarten Zanders <[email protected]> --- arch/arm/src/imx9/Kconfig | 5 ++++- arch/arm/src/imx9/imx9_mu.c | 42 +++++++++++++++++++++--------------------- arch/arm/src/imx9/imx9_mu.h | 38 +++++++++++++++++++------------------- arch/arm/src/imx9/imx9_rptun.c | 8 ++++---- arch/arm/src/imx9/imx9_scmi.c | 12 ++++++------ 5 files changed, 54 insertions(+), 51 deletions(-) diff --git a/arch/arm/src/imx9/Kconfig b/arch/arm/src/imx9/Kconfig index e46d311e34e..e671652653a 100644 --- a/arch/arm/src/imx9/Kconfig +++ b/arch/arm/src/imx9/Kconfig @@ -1003,20 +1003,23 @@ if IMX9_MU config IMX9_MU5 bool "MU5 M7 <-> M33" default y + depends on ARCH_CHIP_IMX95_M7 ---help--- Enable mailbox 5 that operates between M7 and M33 cores config IMX9_MU7 bool "MU7 M7 <-> A55" default n + depends on ARCH_CHIP_IMX95_M7 ---help--- Enable mailbox 7 that operates between M7 and A55 cores config IMX9_MU8 bool "MU8 M7 <-> A55" default n + depends on ARCH_CHIP_IMX95_M7 ---help--- - Enable mailbox 5 that operates between M7 and A55 cores + Enable mailbox 8 that operates between M7 and A55 cores endif # IMX9_MU Configuration diff --git a/arch/arm/src/imx9/imx9_mu.c b/arch/arm/src/imx9/imx9_mu.c index 6ac472a65c0..eecf765ff79 100644 --- a/arch/arm/src/imx9/imx9_mu.c +++ b/arch/arm/src/imx9/imx9_mu.c @@ -27,7 +27,7 @@ #include "imx9_mu.h" #include "arm_internal.h" -#include "hardware/imx95/imx95_memorymap.h" +#include "hardware/imx9_memorymap.h" #include "hardware/imx9_mu.h" #include <debug.h> #include <nuttx/config.h> @@ -106,7 +106,7 @@ static int imx9_mu_interrupt(int irq, void *context, void *args) { if (rsr & (1 << i)) { - uint32_t msg = imx95_mu_receive_msg_non_blocking(dev, i); + uint32_t msg = imx9_mu_receive_msg_non_blocking(dev, i); if (dev->msg_callback) { @@ -145,7 +145,7 @@ static int imx9_mu_interrupt(int irq, void *context, void *args) * Public Functions ****************************************************************************/ -struct imx9_mudev_s *imx95_mu_init(int index) +struct imx9_mudev_s *imx9_mu_init(int index) { struct imx9_mudev_s *priv; @@ -186,29 +186,29 @@ struct imx9_mudev_s *imx95_mu_init(int index) return priv; } -void imx95_mu_subscribe_msg(struct imx9_mudev_s *priv, - uint32_t msg_int_bitfield, - imx9_mu_msg_callback_t callback) +void imx9_mu_subscribe_msg(struct imx9_mudev_s *priv, + uint32_t msg_int_bitfield, + imx9_mu_msg_callback_t callback) { priv->msg_callback = callback; putreg32(msg_int_bitfield & MSG_INT_MASK, IMX9_MU_RCR(priv->mubase)); } -void imx95_mu_subscribe_gpi(struct imx9_mudev_s *priv, - uint32_t gpi_int_enable, - imx9_mu_gpi_callback_t callback) +void imx9_mu_subscribe_gpi(struct imx9_mudev_s *priv, + uint32_t gpi_int_enable, + imx9_mu_gpi_callback_t callback) { priv->gpi_callback = callback; putreg32(gpi_int_enable & GPI_INT_MASK, IMX9_MU_GIER(priv->mubase)); } -void imx95_mu_deinit(struct imx9_mudev_s *priv) +void imx9_mu_deinit(struct imx9_mudev_s *priv) { up_disable_irq(priv->irq); } -int imx95_mu_send_msg_non_blocking(struct imx9_mudev_s *priv, - uint32_t reg_index, uint32_t msg) +int imx9_mu_send_msg_non_blocking(struct imx9_mudev_s *priv, + uint32_t reg_index, uint32_t msg) { assert(reg_index < IMX9_MU_TR_REGARRAY_SIZE); @@ -223,8 +223,8 @@ int imx95_mu_send_msg_non_blocking(struct imx9_mudev_s *priv, return OK; } -void imx95_mu_send_msg(struct imx9_mudev_s *priv, uint32_t reg_index, - uint32_t msg) +void imx9_mu_send_msg(struct imx9_mudev_s *priv, uint32_t reg_index, + uint32_t msg) { assert(reg_index < IMX9_MU_TR_REGARRAY_SIZE); @@ -238,7 +238,7 @@ void imx95_mu_send_msg(struct imx9_mudev_s *priv, uint32_t reg_index, putreg32(msg, IMX9_MU_TR1(priv->mubase) + (reg_index * sizeof(uint32_t))); } -int imx95_mu_has_received_msg(struct imx9_mudev_s *priv, uint32_t reg_index) +int imx9_mu_has_received_msg(struct imx9_mudev_s *priv, uint32_t reg_index) { if ((getreg32(IMX9_MU_RSR(priv->mubase)) & (1UL << reg_index)) == 0UL) { @@ -248,8 +248,8 @@ int imx95_mu_has_received_msg(struct imx9_mudev_s *priv, uint32_t reg_index) return 0; } -uint32_t imx95_mu_receive_msg_non_blocking(struct imx9_mudev_s *priv, - uint32_t reg_index) +uint32_t imx9_mu_receive_msg_non_blocking(struct imx9_mudev_s *priv, + uint32_t reg_index) { assert(reg_index < IMX9_MU_RR_REGARRAY_SIZE); @@ -257,20 +257,20 @@ uint32_t imx95_mu_receive_msg_non_blocking(struct imx9_mudev_s *priv, (reg_index * sizeof(uint32_t))); } -uint32_t imx95_mu_receive_msg(struct imx9_mudev_s *priv, uint32_t reg_index) +uint32_t imx9_mu_receive_msg(struct imx9_mudev_s *priv, uint32_t reg_index) { assert(reg_index < IMX9_MU_RR_REGARRAY_SIZE); /* Wait RX register to be full. */ - while (imx95_mu_has_received_msg(priv, reg_index) == -ENODATA); + while (imx9_mu_has_received_msg(priv, reg_index) == -ENODATA); return getreg32(IMX9_MU_RR1(priv->mubase) + (reg_index * sizeof(uint32_t))); } -int imx95_mu_trigger_interrupts(struct imx9_mudev_s *priv, - uint32_t interrupts) +int imx9_mu_trigger_interrupts(struct imx9_mudev_s *priv, + uint32_t interrupts) { int ret = -ECOMM; uint32_t gcr = getreg32(IMX9_MU_GCR(priv->mubase)); diff --git a/arch/arm/src/imx9/imx9_mu.h b/arch/arm/src/imx9/imx9_mu.h index b929b4f80ad..ceb3b16d06e 100644 --- a/arch/arm/src/imx9/imx9_mu.h +++ b/arch/arm/src/imx9/imx9_mu.h @@ -38,24 +38,24 @@ typedef void (*imx9_mu_gpi_callback_t)(int id, void *arg); * Public Function Prototypes ****************************************************************************/ -struct imx9_mudev_s *imx95_mu_init(int index); -void imx95_mu_subscribe_msg(struct imx9_mudev_s *priv, - uint32_t msg_int_bitfield, - imx9_mu_msg_callback_t callback); -void imx95_mu_subscribe_gpi(struct imx9_mudev_s *priv, - uint32_t gpi_int_enable, - imx9_mu_gpi_callback_t callback); - -void imx95_mu_deinit(struct imx9_mudev_s *priv); -int imx95_mu_send_msg_non_blocking(struct imx9_mudev_s *priv, - uint32_t reg_index, uint32_t msg); -void imx95_mu_send_msg(struct imx9_mudev_s *priv, uint32_t reg_index, - uint32_t msg); -int imx95_mu_has_received_msg(struct imx9_mudev_s *priv, uint32_t reg_index); -uint32_t imx95_mu_receive_msg_non_blocking(struct imx9_mudev_s *priv, - uint32_t reg_index); -uint32_t imx95_mu_receive_msg(struct imx9_mudev_s *priv, uint32_t reg_index); -int imx95_mu_trigger_interrupts(struct imx9_mudev_s *priv, - uint32_t interrupts); +struct imx9_mudev_s *imx9_mu_init(int index); +void imx9_mu_subscribe_msg(struct imx9_mudev_s *priv, + uint32_t msg_int_bitfield, + imx9_mu_msg_callback_t callback); +void imx9_mu_subscribe_gpi(struct imx9_mudev_s *priv, + uint32_t gpi_int_enable, + imx9_mu_gpi_callback_t callback); + +void imx9_mu_deinit(struct imx9_mudev_s *priv); +int imx9_mu_send_msg_non_blocking(struct imx9_mudev_s *priv, + uint32_t reg_index, uint32_t msg); +void imx9_mu_send_msg(struct imx9_mudev_s *priv, uint32_t reg_index, + uint32_t msg); +int imx9_mu_has_received_msg(struct imx9_mudev_s *priv, uint32_t reg_index); +uint32_t imx9_mu_receive_msg_non_blocking(struct imx9_mudev_s *priv, + uint32_t reg_index); +uint32_t imx9_mu_receive_msg(struct imx9_mudev_s *priv, uint32_t reg_index); +int imx9_mu_trigger_interrupts(struct imx9_mudev_s *priv, + uint32_t interrupts); #endif /* __ARCH_ARM_SRC_IMX9_IMX9_MU_H */ diff --git a/arch/arm/src/imx9/imx9_rptun.c b/arch/arm/src/imx9/imx9_rptun.c index 9261ed6f4b0..c63e8f4f959 100644 --- a/arch/arm/src/imx9/imx9_rptun.c +++ b/arch/arm/src/imx9/imx9_rptun.c @@ -217,8 +217,8 @@ static int imx9_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid) ipcinfo("Rptun notify vqid=%ld\n", vqid); - imx95_mu_send_msg(priv->mu, RPMSG_MU_CHANNEL, - vqid << MU_MSG_VQID_BITOFFSET); + imx9_mu_send_msg(priv->mu, RPMSG_MU_CHANNEL, + vqid << MU_MSG_VQID_BITOFFSET); return 0; } @@ -277,14 +277,14 @@ int imx9_rptun_init(const char *shmemname, const char *cpuname) /* Subscribe to MU */ - dev->mu = imx95_mu_init(MU_INSTANCE); + dev->mu = imx9_mu_init(MU_INSTANCE); if (!dev->mu) { ipcerr("ERROR: cannot init mailbox %i!\n", MU_INSTANCE); return ret; } - imx95_mu_subscribe_msg(dev->mu, (1 << RPMSG_MU_CHANNEL), imx9_mu_callback); + imx9_mu_subscribe_msg(dev->mu, (1 << RPMSG_MU_CHANNEL), imx9_mu_callback); /* Configure device */ diff --git a/arch/arm/src/imx9/imx9_scmi.c b/arch/arm/src/imx9/imx9_scmi.c index 0a82291c735..a0e070253b2 100644 --- a/arch/arm/src/imx9/imx9_scmi.c +++ b/arch/arm/src/imx9/imx9_scmi.c @@ -406,8 +406,8 @@ static int32_t imx9_smt_tx(uint32_t smtchannel, uint32_t len, bool callee, case SMT_CRC_CRC32: buf->imp_crc = imx9_crc32((const uint8_t *)&buf->header, len); break; - default:; /* Intentional empty while */ - + default: + ; /* Intentional empty while */ break; } @@ -427,7 +427,7 @@ static int32_t imx9_smt_tx(uint32_t smtchannel, uint32_t len, bool callee, /* Trigger GI interrupt */ - imx95_mu_trigger_interrupts(g_mudev, 1 << db); + imx9_mu_trigger_interrupts(g_mudev, 1 << db); } /* Return status */ @@ -495,8 +495,8 @@ static int32_t imx9_smt_rx(uint32_t smtchannel, uint32_t *len, bool callee) } break; - default:; /* Intentional empty while */ - + default: + ; /* Intentional empty while */ break; } } @@ -1041,7 +1041,7 @@ void imx9_scmi_initialize() /* Configure MU */ - g_mudev = imx95_mu_init(5); + g_mudev = imx9_mu_init(5); } #endif /* CONFIG_IMX9_SCMI */
