lipengfei28 commented on code in PR #16772: URL: https://github.com/apache/nuttx/pull/16772#discussion_r2273592324
########## include/nuttx/pci/pcie_dw.h: ########## @@ -0,0 +1,569 @@ +/**************************************************************************** + * include/nuttx/pci/pcie_dw.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef _PCIE_DESIGNWARE_H +#define _PCIE_DESIGNWARE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <debug.h> + +#include <nuttx/bits.h> +#include <nuttx/kmalloc.h> +#include <nuttx/pci/pci.h> +#include <nuttx/pci/pci_epc.h> +#include <nuttx/pci/pci_epf.h> +#include <nuttx/spinlock.h> +#include <nuttx/list.h> +#include <nuttx/nuttx.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 +#define SZ_4G 0x100000000 + +#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) +#define lower_32_bits(n) ((uint32_t)(n)) +#define readb(a) (*(FAR volatile uint8_t *)(a)) +#define writeb(v,a) (*(FAR volatile uint8_t *)(a) = (v)) +#define readw(a) (*(FAR volatile uint16_t *)(a)) +#define writew(v,a) (*(FAR volatile uint16_t *)(a) = (v)) +#define readl(a) (*(FAR volatile uint32_t *)(a)) +#define writel(v,a) (*(FAR volatile uint32_t *)(a) = (v)) + +#define __bf_shf(x) (ffsll(x) - 1) +#define FIELD_PREP(_mask, _val) (((_val) << __bf_shf(_mask)) & (_mask)) +#define FIELD_GET(_mask, _reg) (((_reg) & (_mask)) >> __bf_shf(_mask)) + +/* DWC PCIe IP-core versions (native support since v4.70a) */ + +#define DW_PCIE_VER_365A 0x3336352a +#define DW_PCIE_VER_460A 0x3436302a +#define DW_PCIE_VER_470A 0x3437302a +#define DW_PCIE_VER_480A 0x3438302a +#define DW_PCIE_VER_490A 0x3439302a +#define DW_PCIE_VER_520A 0x3532302a +#define DW_PCIE_VER_540A 0x3534302a + +#define __dw_pcie_ver_cmp(_pci, _ver, _op) \ + ((_pci)->version _op DW_PCIE_VER_ ## _ver) + +#define dw_pcie_ver_is(_pci, _ver) __dw_pcie_ver_cmp(_pci, _ver, ==) + +#define dw_pcie_ver_is_ge(_pci, _ver) __dw_pcie_ver_cmp(_pci, _ver, >=) + +#define dw_pcie_ver_type_is(_pci, _ver, _type) \ + (__dw_pcie_ver_cmp(_pci, _ver, ==) && \ + __dw_pcie_ver_cmp(_pci, TYPE_ ## _type, ==)) + +#define dw_pcie_ver_type_is_ge(_pci, _ver, _type) \ + (__dw_pcie_ver_cmp(_pci, _ver, ==) && \ + __dw_pcie_ver_cmp(_pci, TYPE_ ## _type, >=)) + +/* DWC PCIe controller capabilities */ + +#define DW_PCIE_CAP_REQ_RES 0 +#define DW_PCIE_CAP_IATU_UNROLL 1 +#define DW_PCIE_CAP_CDM_CHECK 2 + +#define dw_pcie_cap_is(_pci, _cap) \ + test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) + +#define dw_pcie_cap_set(_pci, _cap) \ + set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) + +/* Parameters for the waiting for link up routine */ + +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_SLEEP_MS 90 + +/* Parameters for the waiting for iATU enabled routine */ + +#define LINK_WAIT_MAX_IATU_RETRIES 5 +#define LINK_WAIT_IATU 9 + +/* Synopsys-specific PCIe configuration registers */ + +#define PCIE_PORT_FORCE 0x708 +#define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) + +#define PCIE_PORT_AFR 0x70C Review Comment: done ########## include/nuttx/pci/pcie_dw.h: ########## @@ -0,0 +1,569 @@ +/**************************************************************************** + * include/nuttx/pci/pcie_dw.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef _PCIE_DESIGNWARE_H +#define _PCIE_DESIGNWARE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <debug.h> + +#include <nuttx/bits.h> +#include <nuttx/kmalloc.h> +#include <nuttx/pci/pci.h> +#include <nuttx/pci/pci_epc.h> +#include <nuttx/pci/pci_epf.h> +#include <nuttx/spinlock.h> +#include <nuttx/list.h> +#include <nuttx/nuttx.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 +#define SZ_4G 0x100000000 + +#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) +#define lower_32_bits(n) ((uint32_t)(n)) +#define readb(a) (*(FAR volatile uint8_t *)(a)) +#define writeb(v,a) (*(FAR volatile uint8_t *)(a) = (v)) +#define readw(a) (*(FAR volatile uint16_t *)(a)) +#define writew(v,a) (*(FAR volatile uint16_t *)(a) = (v)) +#define readl(a) (*(FAR volatile uint32_t *)(a)) +#define writel(v,a) (*(FAR volatile uint32_t *)(a) = (v)) + +#define __bf_shf(x) (ffsll(x) - 1) +#define FIELD_PREP(_mask, _val) (((_val) << __bf_shf(_mask)) & (_mask)) +#define FIELD_GET(_mask, _reg) (((_reg) & (_mask)) >> __bf_shf(_mask)) + +/* DWC PCIe IP-core versions (native support since v4.70a) */ + +#define DW_PCIE_VER_365A 0x3336352a +#define DW_PCIE_VER_460A 0x3436302a +#define DW_PCIE_VER_470A 0x3437302a +#define DW_PCIE_VER_480A 0x3438302a +#define DW_PCIE_VER_490A 0x3439302a +#define DW_PCIE_VER_520A 0x3532302a +#define DW_PCIE_VER_540A 0x3534302a + +#define __dw_pcie_ver_cmp(_pci, _ver, _op) \ + ((_pci)->version _op DW_PCIE_VER_ ## _ver) + +#define dw_pcie_ver_is(_pci, _ver) __dw_pcie_ver_cmp(_pci, _ver, ==) + +#define dw_pcie_ver_is_ge(_pci, _ver) __dw_pcie_ver_cmp(_pci, _ver, >=) + +#define dw_pcie_ver_type_is(_pci, _ver, _type) \ + (__dw_pcie_ver_cmp(_pci, _ver, ==) && \ + __dw_pcie_ver_cmp(_pci, TYPE_ ## _type, ==)) + +#define dw_pcie_ver_type_is_ge(_pci, _ver, _type) \ + (__dw_pcie_ver_cmp(_pci, _ver, ==) && \ + __dw_pcie_ver_cmp(_pci, TYPE_ ## _type, >=)) + +/* DWC PCIe controller capabilities */ + +#define DW_PCIE_CAP_REQ_RES 0 +#define DW_PCIE_CAP_IATU_UNROLL 1 +#define DW_PCIE_CAP_CDM_CHECK 2 + +#define dw_pcie_cap_is(_pci, _cap) \ + test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) + +#define dw_pcie_cap_set(_pci, _cap) \ + set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) + +/* Parameters for the waiting for link up routine */ + +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_SLEEP_MS 90 + +/* Parameters for the waiting for iATU enabled routine */ + +#define LINK_WAIT_MAX_IATU_RETRIES 5 +#define LINK_WAIT_IATU 9 + +/* Synopsys-specific PCIe configuration registers */ + +#define PCIE_PORT_FORCE 0x708 +#define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) + +#define PCIE_PORT_AFR 0x70C +#define PORT_AFR_N_FTS_MASK GENMASK(15, 8) +#define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n) +#define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16) +#define PORT_AFR_CC_N_FTS(n) FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n) +#define PORT_AFR_ENTER_ASPM BIT(30) +#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24 +#define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24) +#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27 +#define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27) + +#define PCIE_PORT_LINK_CONTROL 0x710 +#define PORT_LINK_DLL_LINK_EN BIT(5) +#define PORT_LINK_FAST_LINK_MODE BIT(7) +#define PORT_LINK_MODE_MASK GENMASK(21, 16) +#define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) +#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) +#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) +#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) +#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) + +#define PCIE_PORT_LANE_SKEW 0x714 +#define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) + +#define PCIE_PORT_DEBUG0 0x728 +#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f +#define PORT_LOGIC_LTSSM_STATE_L0 0x11 +#define PCIE_PORT_DEBUG1 0x72C +#define PCIE_PORT_DEBUG1_LINK_UP BIT(4) +#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29) + +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C +#define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0) +#define PORT_LOGIC_SPEED_CHANGE BIT(17) +#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) +#define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n) +#define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) +#define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2) +#define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) +#define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) + +#define PCIE_MSI_ADDR_LO 0x820 +#define PCIE_MSI_ADDR_HI 0x824 +#define PCIE_MSI_INTR0_ENABLE 0x828 +#define PCIE_MSI_INTR0_MASK 0x82C +#define PCIE_MSI_INTR0_STATUS 0x830 + +#define GEN3_RELATED_OFF 0x890 +#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) +#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13) +#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) +#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 +#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) +#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT 0x1 + +#define GEN3_EQ_CONTROL_OFF 0x8A8 +#define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0) +#define GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE BIT(4) +#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC GENMASK(23, 8) +#define GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL BIT(24) + +#define GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x8AC +#define GEN3_EQ_FMDC_T_MIN_PHASE23 GENMASK(4, 0) +#define GEN3_EQ_FMDC_N_EVALS GENMASK(9, 5) +#define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA GENMASK(13, 10) +#define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA GENMASK(17, 14) + +#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 +#define PORT_MLTI_UPCFG_SUPPORT BIT(7) + +#define PCIE_VERSION_NUMBER 0x8F8 +#define PCIE_VERSION_TYPE 0x8FC + +/* iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each + * iATU region CSRs had been indirectly accessible by means of the dedicated + * viewport selector. The iATU/eDMA CSRs space was re-designed in DWC PCIe + * v4.80a in a way so the viewport was unrolled into the directly accessible + * iATU/eDMA CSRs space. + */ + +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_DIR_IB BIT(31) +#define PCIE_ATU_REGION_DIR_OB 0 +#define PCIE_ATU_VIEWPORT_BASE 0x904 +#define PCIE_ATU_UNROLL_BASE(dir, index) \ + (((index) << 9) | ((dir == PCIE_ATU_REGION_DIR_IB) ? BIT(8) : 0)) +#define PCIE_ATU_VIEWPORT_SIZE 0x2C +#define PCIE_ATU_REGION_CTRL1 0x000 +#define PCIE_ATU_INCREASE_REGION_SIZE BIT(13) +#define PCIE_ATU_TYPE_MEM 0x0 +#define PCIE_ATU_TYPE_IO 0x2 +#define PCIE_ATU_TYPE_CFG0 0x4 +#define PCIE_ATU_TYPE_CFG1 0x5 +#define PCIE_ATU_TYPE_MSG 0x10 +#define PCIE_ATU_TD BIT(8) +#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20) +#define PCIE_ATU_REGION_CTRL2 0x004 +#define PCIE_ATU_ENABLE BIT(31) +#define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) +#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) +#define PCIE_ATU_LOWER_BASE 0x008 +#define PCIE_ATU_UPPER_BASE 0x00C +#define PCIE_ATU_LIMIT 0x010 +#define PCIE_ATU_LOWER_TARGET 0x014 +#define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x) +#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x) +#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x) +#define PCIE_ATU_UPPER_TARGET 0x018 +#define PCIE_ATU_UPPER_LIMIT 0x020 + +#define PCIE_MISC_CONTROL_1_OFF 0x8BC +#define PCIE_DBI_RO_WR_EN BIT(0) + +#define PCIE_MSIX_DOORBELL 0x948 +#define PCIE_MSIX_DOORBELL_PF_SHIFT 24 + +#define PCIE_DMA_VIEWPORT_BASE 0x970 +#define PCIE_DMA_UNROLL_BASE 0x80000 +#define PCIE_DMA_CTRL 0x008 +#define PCIE_DMA_NUM_WR_CHAN GENMASK(3, 0) +#define PCIE_DMA_NUM_RD_CHAN GENMASK(19, 16) + +#define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20 +#define PCIE_PL_CHK_REG_CHK_REG_START BIT(0) +#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1) +#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERR BIT(16) +#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17) +#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18) + +#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28 + +/* 16.0 GT/s (Gen 4) lane margining register definitions + */ + +#define GEN4_LANE_MARGINING_1_OFF 0xB80 +#define MARGINING_MAX_VOLTAGE_OFFSET GENMASK(29, 24) +#define MARGINING_NUM_VOLTAGE_STEPS GENMASK(22, 16) +#define MARGINING_MAX_TIMING_OFFSET GENMASK(13, 8) +#define MARGINING_NUM_TIMING_STEPS GENMASK(5, 0) + +#define GEN4_LANE_MARGINING_2_OFF 0xB84 +#define MARGINING_IND_ERROR_SAMPLER BIT(28) +#define MARGINING_SAMPLE_REPORTING_METHOD BIT(27) +#define MARGINING_IND_LEFT_RIGHT_TIMING BIT(26) +#define MARGINING_IND_UP_DOWN_VOLTAGE BIT(25) +#define MARGINING_VOLTAGE_SUPPORTED BIT(24) +#define MARGINING_MAXLANES GENMASK(20, 16) +#define MARGINING_SAMPLE_RATE_TIMING GENMASK(13, 8) +#define MARGINING_SAMPLE_RATE_VOLTAGE GENMASK(5, 0) + +/* iATU Unroll-specific register definitions + * From 4.80 core version the address translation will be made by unroll + */ + +#define PCIE_ATU_UNR_REGION_CTRL1 0x00 +#define PCIE_ATU_UNR_REGION_CTRL2 0x04 +#define PCIE_ATU_UNR_LOWER_BASE 0x08 +#define PCIE_ATU_UNR_UPPER_BASE 0x0C +#define PCIE_ATU_UNR_LOWER_LIMIT 0x10 +#define PCIE_ATU_UNR_LOWER_TARGET 0x14 +#define PCIE_ATU_UNR_UPPER_TARGET 0x18 +#define PCIE_ATU_UNR_UPPER_LIMIT 0x20 + +/* RAS-DES register definitions + */ +#define PCIE_RAS_DES_EVENT_COUNTER_CONTROL 0x8 +#define EVENT_COUNTER_ALL_CLEAR 0x3 +#define EVENT_COUNTER_ENABLE_ALL 0x7 +#define EVENT_COUNTER_ENABLE_SHIFT 2 +#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0) +#define EVENT_COUNTER_EVENT_SEL_SHIFT 16 +#define EVENT_COUNTER_EVENT_Tx_L0S 0x2 +#define EVENT_COUNTER_EVENT_Rx_L0S 0x3 +#define EVENT_COUNTER_EVENT_L1 0x5 +#define EVENT_COUNTER_EVENT_L1_1 0x7 +#define EVENT_COUNTER_EVENT_L1_2 0x8 +#define EVENT_COUNTER_GROUP_SEL_SHIFT 24 +#define EVENT_COUNTER_GROUP_5 0x5 + +#define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc + +/* The default address offset between dbi_base and atu_base. Root + * controller drivers are not required to initialize atu_base + * if the offset matches this default; the driver core + * automatically derives atu_base From dbi_base using this offset, + * if atu_base not set. + */ + +#define DEFAULT_DBI_ATU_OFFSET (0x3 << 20) +#define DEFAULT_DBI_DMA_OFFSET PCIE_DMA_UNROLL_BASE + +#define MAX_MSI_IRQS 256 +#define MAX_MSI_IRQS_PER_CTRL 32 +#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) +#define MSI_REG_CTRL_BLOCK_SIZE 12 +#define MSI_DEF_NUM_VECTORS 32 + +/* Maximum number of inbound/outbound iATUs */ + +#define MAX_IATU_IN 256 +#define MAX_IATU_OUT 256 + +#define DMA_LLP_MEM_SIZE PAGE_SIZE + +#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie_s, pp) + +#define to_dw_pcie_from_ep(endpoint) \ + container_of((endpoint), struct dw_pcie_s, ep) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct dw_pcie_ep_s +{ + FAR struct pci_epc_ctrl_s *epc; + struct list_node func_list; + FAR const struct dw_pcie_ep_ops *ops; + uint64_t phys_base; + size_t addr_size; + FAR void *dma_addr; + size_t dma_len; + size_t page_size; + uint8_t bar_to_atu[PCI_STD_NUM_BARS]; + FAR uintptr_t *outbound_addr; + FAR unsigned long *ib_window_map; + FAR unsigned long *ob_window_map; + FAR void *msi_mem; + uint64_t msi_mem_phys; + FAR struct pci_epf_bar_s *epf_bar[PCI_STD_NUM_BARS]; +}; + +struct dw_pcie_rp_s +{ + bool has_msi_ctrl:1; + bool cfg0_io_shared:1; + uint64_t cfg0_base; + FAR void *va_cfg0_base; + uint32_t cfg0_size; + uintptr_t io_base; + uint64_t io_bus_addr; + uint32_t io_size; + int irq; + FAR const struct dw_pcie_host_ops *ops; + int msi_irq[MAX_MSI_CTRLS]; + uint64_t msi_data; + uint32_t num_vectors; + uint32_t irq_mask[MAX_MSI_CTRLS]; + FAR struct pci_host_bridge *bridge; + spinlock_t lock; + DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); + bool use_atu_msg; + int msg_atu_index; + FAR struct resource *msg_res; +}; + +struct dw_pcie_s +{ + FAR void *dbi_base; + FAR uintptr_t dbi_phys_addr; + FAR void *dbi_base2; + FAR void *atu_base; + uintptr_t atu_phys_addr; + size_t atu_size; + uint32_t num_ib_windows; + uint32_t num_ob_windows; + uint32_t region_align; + uint64_t region_limit; + struct dw_pcie_rp_s pp; + struct dw_pcie_ep_s ep; + FAR const struct dw_pcie_ops_s *ops; + uint32_t version; + uint32_t type; + unsigned long caps; + int num_lanes; + int max_link_speed; + uint8_t n_fts[2]; + FAR void *priv; +}; + +enum dw_pcie_ltssm +{ + /* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */ + + DW_PCIE_LTSSM_DETECT_QUIET = 0x0, + DW_PCIE_LTSSM_DETECT_ACT = 0x1, + DW_PCIE_LTSSM_L0 = 0x11, + DW_PCIE_LTSSM_L2_IDLE = 0x15, + + DW_PCIE_LTSSM_UNKNOWN = 0xffffffff, +}; + +struct dw_pcie_ob_atu_cfg_s +{ + int index; + int type; + uint8_t funcno; + uint8_t code; + uint8_t routing; + uint64_t cpu_addr; + uint64_t pci_addr; + uint64_t size; +}; + +struct dw_pcie_host_ops +{ + CODE int (*init)(FAR struct dw_pcie_rp_s *pp); + CODE void (*deinit)(FAR struct dw_pcie_rp_s *pp); + CODE void (*post_init)(FAR struct dw_pcie_rp_s *pp); + CODE int (*msi_init)(FAR struct dw_pcie_rp_s *pp); + CODE void (*pme_turn_off)(FAR struct dw_pcie_rp_s *pp); +}; + +struct dw_pcie_ep_ops +{ + CODE void (*pre_init)(FAR struct dw_pcie_ep_s *ep); + CODE void (*init)(FAR struct dw_pcie_ep_s *ep); + CODE int (*raise_irq)(FAR struct dw_pcie_ep_s *ep, uint8_t funcno, + unsigned int type, uint16_t interrupt_num); + CODE const FAR struct pci_epc_features_s *(*get_features) + (FAR struct dw_pcie_ep_s *ep); + CODE uint32_t (*get_dbi_offset)(FAR struct dw_pcie_ep_s *ep, + uint8_t funcno); + CODE uint32_t (*get_dbi2_offset)(FAR struct dw_pcie_ep_s *ep, + uint8_t funcno); +}; + +struct dw_pcie_ep_func_s +{ + struct list_node list; + uint8_t funcno; + uint8_t msi_cap; /* MSI capability offset */ + uint8_t msix_cap; /* MSI-X capability offset */ +}; + +struct dw_pcie_ops_s +{ + CODE uint64_t (*cpu_addr_fixup)(FAR struct dw_pcie_s *pcie, + uint64_t cpu_addr); + CODE uint32_t (*read_dbi)(FAR struct dw_pcie_s *pcie, FAR void *base, + uint32_t reg, size_t size); + CODE void (*write_dbi)(FAR struct dw_pcie_s *pcie, FAR void *base, + uint32_t reg, size_t size, uint32_t val); + CODE void (*write_dbi2)(FAR struct dw_pcie_s *pcie, FAR void *base, + uint32_t reg, size_t size, uint32_t val); + CODE int (*link_up)(FAR struct dw_pcie_s *pcie); + CODE enum dw_pcie_ltssm (*get_ltssm)(FAR struct dw_pcie_s *pcie); + CODE int (*start_link)(FAR struct dw_pcie_s *pcie); + CODE void (*stop_link)(FAR struct dw_pcie_s *pcie); +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int dw_pcie_get_resources(FAR struct dw_pcie_s *pci); Review Comment: done -- This is an automated message from the Apache Git Service. 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