gpoulios commented on code in PR #16729:
URL: https://github.com/apache/nuttx/pull/16729#discussion_r2209402819
##########
drivers/misc/optee.c:
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@@ -345,6 +346,10 @@ optee_shm_to_page_list(FAR struct optee_shm *shm, FAR
uintptr_t *list_pa)
*list_pa = optee_va_to_pa(list) | pgoff;
}
+#ifndef CONFIG_ARCH_USE_MMU
Review Comment:
It **_is_** a supported configuration, even though uncommon:
1) The document you cite states that in the case of MMU off (emphasis mine):
> _Unexpected data cache hit behavior is **implementation defined**._
2) Please have a look at [this
thread](https://community.arm.com/support-forums/f/architectures-and-processors-forum/8908/a8-keeping-cache-enabled-and-mmu-disabled),
and in particular the [selected
answer](https://community.arm.com/support-forums/f/architectures-and-processors-forum/8908/a8-keeping-cache-enabled-and-mmu-disabled/29759)
by an Arm employee at the bottom (again, emphasis mine):
> _There is absolutely no point in running without the MMU enabled, **except
if you are EXTREMELY resource-constrained and can't spare the memory to write
the tables** (you only need 16KiB, though, for the bare essentials at 1MB and
16MB granularity)._
Well, in our case, we **_are_** extremely resource constrained (and we've
found that in NuttX, the tables take up ~~slightly~~ significantly more than
16KiB, but even if so, we can't spare those 16KiB).
and:
> _Whether the caches are 'enabled' [...] or not, **every request goes
through the memory system hierarchy in order a non-cacheable access passes
through the L1 cache controller, which may pass it to the L2 cache controller,
and so on**._
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