xiaoxiang781216 commented on code in PR #16729:
URL: https://github.com/apache/nuttx/pull/16729#discussion_r2209008333


##########
drivers/misc/optee.c:
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@@ -345,6 +346,10 @@ optee_shm_to_page_list(FAR struct optee_shm *shm, FAR 
uintptr_t *list_pa)
       *list_pa = optee_va_to_pa(list) | pgoff;
     }
 
+#ifndef CONFIG_ARCH_USE_MMU

Review Comment:
   but MMU is still enable, otherwise the code doesn't need program MMU related 
registers. I never saw Cortex-A chip doesn't enable MMU in proudction since the 
cachable configuration come from MMU entry.
   The real difference is whether config MMU to flat virtual address space(flat 
build) or overlapped virtual address space(kernel build).
   But either config is the pure software favorite, I am wondering why it 
impact the cache coherence between normal and secure world.



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