kywwilson11 opened a new pull request, #16706:
URL: https://github.com/apache/nuttx/pull/16706

   ## Summary
   
   - Add `stm32_dma.[ch]` to the STM32H5 build when `CONFIG_STM32H5_DMA=y`  
   - Include `stm32h56x_dmasigmap.h` and update `stm32_gpdma.h` with H5 
register and IRQ defs  
   - Expose ADC DMA options in `arch/arm/src/stm32h5/Kconfig`:  
     - `CONFIG_STM32H5_ADCx_DMA`  
     - `CONFIG_STM32H5_ADCx_DMA_BATCH`  
     - `CONFIG_STM32H5_ADCx_DMA_CFG`  
     - `STM32H5_ADC_MAX_SAMPLES`  
   - Extend `stm32_adc.[ch]` to track a `hasdma` flag per ADC (default `false`) 
 
   - Set `hasdma = true` only when DMA is enabled; skip IRQ registration if 
`hasdma`  
   - Disable ADC IRQs when DMA is active to avoid mixed-mode conflicts  
   - Tidy formatting, align comments, and clean up whitespace across ADC and 
DMA files  
   
   ## Impact
   
   - **New DMA support** for STM32H5 ADCs (one-shot, circular, batch)  
   - **Config changes**  
     - Must enable both `CONFIG_STM32H5_DMA` and per-ADC 
`CONFIG_STM32H5_ADCx_DMA` to use DMA  
     - Default (no-DMA) stays the same  
   - **Build & ABI**  
     - `stm32_dma.c` only included under `CONFIG_STM32H5_DMA`  
     - No public API changes; `hasdma` is internal  
   - **Runtime**  
     - ADCs without DMA still use IRQs  
     - Mixed setups now work without spurious IRQs  
   - **Compatibility & docs**  
     - Backward-compatible for existing users  
     - No docs changed; consider updating STM32H5 board guide  
   - **Security & stability**  
     - No security impact; new paths gated by CONFIG flags and tested  
   
   ## Testing
   
   - One-shot mode verified  
   - Circular mode with linked-list (in `stm32_dma.c`) verified  
   - `dmabatch` verified with 1 Hz timer trigger; batch size multiplies sample 
period  
   - HW: Channel 3→GND, Channel 10→3.3 V  
   - Used ADC example app; circular mode output:
   
       ```
       NuttShell (NSH) NuttX-12.10.0
       nsh> adc
       adc_main: g_adcstate.count: 4
       adc_main: Hardware initialized. Opening the ADC device: /dev/adc0
       Sample:
       1: channel: 3 value: 0
       2: channel: 10 value: 4080
       Sample:
       1: channel: 3 value: 14
       2: channel: 10 value: 4095
       Sample:
       1: channel: 3 value: 0
       2: channel: 10 value: 4095
       Sample:
       1: channel: 3 value: 11
       2: channel: 10 value: 4091
       nsh>
       ```
   


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