jasonbu opened a new pull request, #16671: URL: https://github.com/apache/nuttx/pull/16671
## Summary When we locate the internal ostest sometime failure, find this bug. If atomic_try_cmpxchg_xxxx runs on LL/SC architectures (e.g.ARMv7, ARMv8, RISC-V), the weak CAS expands to a single LDREX/STREX pair. If the CPU takes an IRQ/FIQ/SVC between the two instructions, hardware performs an implicit CLREX and the following STREX returns 1, therefore atomic_try_cmpxchg_xxxx return failure even though *addr* still holds the expected value. [arm/CLREX](https://developer.arm.com/documentation/dui0646/c/The-Cortex-M7-Instruction-Set/Memory-access-instructions/CLREX) Tested by ```C int main(int argc, FAR char *argv[]) { pthread_rwlock_t rw_lock; int i = 0; while(true) { printf("%d\n", i++); ASSERT(pthread_rwlock_init(&rw_lock, NULL) == 0); ASSERT(pthread_rwlock_trywrlock(&rw_lock) == 0); ASSERT(pthread_rwlock_unlock(&rw_lock) == 0); ASSERT(pthread_rwlock_trywrlock(&rw_lock) == 0); ASSERT(pthread_rwlock_tryrdlock(&rw_lock) == EBUSY); ASSERT(pthread_rwlock_tryrdlock(&rw_lock) == EBUSY); ASSERT(pthread_rwlock_unlock(&rw_lock) == 0); } return 0; } ``` If tickless not enabled, will quickly(<30s) failed. before fix. And will never fail again after fixed. ## Impact Before Fix, the ostest sometimes report first rwlock_trywrlock failed even when first rwlock_init. After Fix, Add a check again even atomic_try_cmpxchg_acquire report failure, problem fixed. ## Testing CI-test, internal board, qemu-mps3 ostest. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
