snikeguo opened a new issue, #16400:
URL: https://github.com/apache/nuttx/issues/16400
### Description
usercode:
```
printf("USER MAIN!!!\n");
boardctl(BOARDIOC_INIT, 0); //mount /dev/mmcsd0 ->/mnt/sd0
printf("USER MAIN:open mnt/sd0/2.txt,O_RDWR|O_CREAT,666\n");
int fd=open("/mnt/sd0/2.txt",O_RDWR|O_CREAT,666);
if(fd<0)
{
printf("open file error\n");
return -1;
}
printf("USER MAIN:write mnt/sd0/2.txt,hello world\n");
write(fd,"hello world\n",12);
printf("USER MAIN:close fd\n");
close(fd);
printf("USER MAIN:open mnt/sd0/2.txt,O_RDONLY,666\n");
fd=open("/mnt/sd0/2.txt",O_RDONLY,666);
if(fd<0)
{
printf("USER MAIN:open file error\n");
return -1;
}
char buf[20];
int readed_size=read(fd,buf,sizeof(buf));
close(fd);
printf("readed_size=%d\n",readed_size);
int ret=nx_umount2("/mnt/sd0", 0);
```
console log:
```
USER MAIN!!!
stm32_sdio_initialize: Initializing SDIO slot 0
stm32_setclkcr: CLKCR: 0003003f PWR: 00000003
stm32_reset: CLCKR: 0003003f POWER: 00000003
stm32_sdio_initialize: Bind SDIO to the MMC/SD driver, minor=0
mmcsd_slotinitialize: minor: 0
mmcsd_hwinitialize: DMA supported: 1
mmcsd_hwinitialize: Attached MMC/SD interrupts
stm32_registercallback: Register 0xc000c965(0xc08084f8)
stm32_callbackenable: eventset: 02
stm32_callback: Callback 0xc000c965(0xc08084f8) cbevents: 02 cdstatus: 00
mmcsd_slotinitialize: MMC/SD slot is empty
mmcsd_slotinitialize: MMC: /dev/mmcsd0 0KB 1-bit backwards compatibility mode
stm32_sdio_initialize: Successfully bound SDIO to the MMC/SD driver
stm32_sdio_initialize: Card detect : 1
sdio_mediachange: cdstatus OLD: 00 NEW: 01
stm32_callback: Callback 0xc000c965(0xc08084f8) cbevents: 02 cdstatus: 01
stm32_callback: Callback to 0xc000c965(0xc08084f8)
mmcsd_mediachange: arg: 0xc08084f8
mmcsd_probe: type: 0 probed: 0
mmcsd_removed: type: 0 present: 1
mmcsd_widebus: No card inserted.
stm32_setclkcr: CLKCR: 0003003f PWR: 00000003
stm32_setclkcr: CLKCR: 0003003f PWR: 00000003
mmcsd_probe: Card present. Probing....
mmcsd_cardidentify: Identifying card...
stm32_setclkcr: CLKCR: 0003003f PWR: 00000003
stm32_sendcmd: cmd: 00000000 arg: f0f0f0f0 regval: 00001000 enabled irq:
00000000
stm32_sendcmd: cmd: 00000000 arg: 00000000 regval: 00001000 enabled irq:
00000000
stm32_sendcmd: cmd: 00000208 arg: 000001aa regval: 00001108 enabled irq:
00000000
mmcsd_cardidentify: SD V2.x card
stm32_sendcmd: cmd: 00000077 arg: 00000000 regval: 00001137 enabled irq:
00000000
stm32_sendcmd: cmd: 00000129 arg: 40100000 regval: 00001129 enabled irq:
00000000
mmcsd_cardidentify: R3: 40ff8000
stm32_sendcmd: cmd: 00000077 arg: 00000000 regval: 00001137 enabled irq:
00000000
stm32_sendcmd: cmd: 00000129 arg: 40100000 regval: 00001129 enabled irq:
00000000
mmcsd_cardidentify: R3: c0ff8000
mmcsd_cardidentify: SD V2.x card with block addressing
mmcsd_probe: SD version 2.x with block addressing.
stm32_sendcmd: cmd: 000000c2 arg: 00000000 regval: 00001302 enabled irq:
00000000
mmcsd_decode_cid: mid: fe cbx: 0 oid: 32 pnm: SD prv: 0 psn: 0001ed01 mdt:
87 crc: 53
stm32_sendcmd: cmd: 000001c3 arg: 00000000 regval: 00001103 enabled irq:
00000000
mmcsd_sdinitialize: RCA: 0001
stm32_sendcmd: cmd: 0000004d arg: 00010000 regval: 0000110d enabled irq:
00000000
stm32_sendcmd: cmd: 000000c9 arg: 00010000 regval: 00001309 enabled irq:
00000000
mmcsd_decode_csd: CSD:
mmcsd_decode_csd: CSD_STRUCTURE: 1 SPEC_VERS: 0 (MMC)
mmcsd_decode_csd: TAAC {TIME_UNIT: 6 TIME_VALUE: 1} NSAC: 0
mmcsd_decode_csd: TRAN_SPEED {TRANSFER_RATE_UNIT: 2 TIME_VALUE: 6}
mmcsd_decode_csd: CCC: 1461
mmcsd_decode_csd: READ_BL_LEN: 9 READ_BL_PARTIAL: 0
mmcsd_decode_csd: WRITE_BLK_MISALIGN: 0 READ_BLK_MISALIGN: 0
mmcsd_decode_csd: DSR_IMP: 0
mmcsd_decode_csd: SD Block Addressing:
mmcsd_decode_csd: C_SIZE: 29819 SD_ER_BLK_EN: 1
mmcsd_decode_csd: SD_SECTOR_SIZE: 127 SD_WP_GRP_SIZE: 0
mmcsd_decode_csd: WP_GRP_EN: 0 MMC DFLT_ECC: 0 (MMC) R2W_FACTOR: 2
mmcsd_decode_csd: WRITE_BL_LEN: 9 WRITE_BL_PARTIAL: 0
mmcsd_decode_csd: FILE_FORMAT_GROUP: 0 COPY: 0
mmcsd_decode_csd: PERM_WRITE_PROTECT: 0 TMP_WRITE_PROTECT: 0
mmcsd_decode_csd: FILE_FORMAT: 0 ECC: 0 (MMC) CRC: 78
mmcsd_decode_csd: Capacity: 15267840Kb, Block size: 512b, nblocks: 30535680
wrprotect: 0
stm32_sendcmd: cmd: 00000087 arg: 00010000 regval: 00001107 enabled irq:
00000000
stm32_setclkcr: CLKCR: 00031003 PWR: 00000003
stm32_sendcmd: cmd: 00000050 arg: 00000008 regval: 00001110 enabled irq:
00000000
stm32_sendcmd: cmd: 00000077 arg: 00010000 regval: 00001137 enabled irq:
0000012a
stm32_sendcmd: cmd: 00000473 arg: 00000000 regval: 00001173 enabled irq:
0000012a
mmcsd_decode_scr: SCR:
mmcsd_decode_scr: SCR_STRUCTURE: 0 SD_VERSION: 2
mmcsd_decode_scr: DATA_STATE_AFTER_ERASE: 1 SD_SECURITY: 0 SD_BUS_WIDTHS: 5
mmcsd_decode_scr: Manufacturing data: 00000000
mmcsd_probe: Capacity: 15267840 Kbytes
stm32_callbackenable: eventset: 01
stm32_callback: Callback 0xc000c965(0xc08084f8) cbevents: 01 cdstatus: 01
find_blockdriver: pathname="/dev/mmcsd0"
mmcsd_open: Entry
mmcsd_geometry: Entry
mmcsd_geometry: available: true mediachanged: true writeenabled: true
mmcsd_geometry: nsectors: 30535680 sectorsize: 512
mmcsd_read: startsector: 0 nsectors: 1 sectorsize: 512
mmcsd_readsingle: startblock=0
mmcsd_readsingle: offset=0
stm32_sendcmd: cmd: 00000050 arg: 00000200 regval: 00001110 enabled irq:
00000000
stm32_sendcmd: cmd: 00000451 arg: 00000000 regval: 00001151 enabled irq:
0000012a
mmcsd_read: startsector: 1 nsectors: 1 sectorsize: 512
mmcsd_readsingle: startblock=1
mmcsd_readsingle: offset=1
stm32_sendcmd: cmd: 00000451 arg: 00000001 regval: 00001151 enabled irq:
0000012a
fat_mount: FAT32:
fat_mount: HW sector size: 512
fat_mount: sectors: 30535680
fat_mount: FAT reserved: 2978
fat_mount: sectors: 30535680
fat_mount: start sector: 2978
fat_mount: root sector: 2
fat_mount: root entries: 0
fat_mount: data sector: 32768
fat_mount: FSINFO sector: 1
fat_mount: Num FATs: 2
fat_mount: FAT sectors: 14895
fat_mount: sectors/cluster: 16
fat_mount: max clusters: 1906432
fat_mount: FSI free count 1906427
fat_mount: next free 7
USER MAIN:open mnt/sd0/2.txt,O_RDWR|O_CREAT,666
mmcsd_geometry: Entry
mmcsd_geometry: available: true mediachanged: false writeenabled: true
mmcsd_geometry: nsectors: 30535680 sectorsize: 512
mmcsd_read: startsector: 32768 nsectors: 1 sectorsize: 512
mmcsd_readsingle: startblock=32768
mmcsd_readsingle: offset=32768
stm32_sendcmd: cmd: 00000451 arg: 00008000 regval: 00001151 enabled irq:
0000012a
USER MAIN:write mnt/sd0/2.txt,hello world
mmcsd_geometry: Entry
mmcsd_geometry: available: true mediachanged: false writeenabled: true
mmcsd_geometry: nsectors: 30535680 sectorsize: 512
mmcsd_write: startsector: 32768 nsectors: 1 sectorsize: 512
mmcsd_writesingle: startblock=32768
mmcsd_writesingle: offset=32768
stm32_sendcmd: cmd: 00001458 arg: 00008000 regval: 00001158 enabled irq:
0000011a
mmcsd_read: startsector: 2978 nsectors: 1 sectorsize: 512
mmcsd_readsingle: startblock=2978
stm32_sendcmd: cmd: 0000004d arg: 00010000 regval: 0000110d enabled irq:
00000000
mmcsd_readsingle: offset=2978
stm32_sendcmd: cmd: 00000451 arg: 00000ba2 regval: 00001151 enabled irq:
0000012a
fat_currentsector: position=0 currentsector=32864 sectorsincluster=16
USER MAIN:close fd
mmcsd_geometry: Entry
mmcsd_geometry: available: true mediachanged: false writeenabled: true
mmcsd_geometry: nsectors: 30535680 sectorsize: 512
mmcsd_write: startsector: 32864 nsectors: 1 sectorsize: 512
mmcsd_writesingle: startblock=32864
mmcsd_writesingle: offset=32864
stm32_sendcmd: cmd: 00001458 arg: 00008060 regval: 00001158 enabled irq:
0000011a
mmcsd_write: startsector: 2978 nsectors: 1 sectorsize: 512
mmcsd_writesingle: startblock=2978
stm32_sendcmd: cmd: 0000004d arg: 00010000 regval: 0000110d enabled irq:
00000000
mmcsd_writesingle: offset=2978
stm32_sendcmd: cmd: 00001458 arg: 00000ba2 regval: 00001158 enabled irq:
0000011a
mmcsd_write: startsector: 17873 nsectors: 1 sectorsize: 512
mmcsd_writesingle: startblock=17873
stm32_sendcmd: cmd: 0000004d arg: 00010000 regval: 0000110d enabled irq:
00000000
mmcsd_writesingle: offset=17873
stm32_sendcmd: cmd: 00001458 arg: 000045d1 regval: 00001158 enabled irq:
0000011a
mmcsd_read: startsector: 32768 nsectors: 1 sectorsize: 512
mmcsd_readsingle: startblock=32768
stm32_sendcmd: cmd: 0000004d arg: 00010000 regval: 0000110d enabled irq:
00000000
mmcsd_readsingle: offset=32768
stm32_sendcmd: cmd: 00000451 arg: 00008000 regval: 00001151 enabled irq:
0000012a
mmcsd_write: startsector: 32768 nsectors: 1 sectorsize: 512
mmcsd_writesingle: startblock=32768
mmcsd_writesingle: offset=32768
stm32_sendcmd: cmd: 00001458 arg: 00008000 regval: 00001158 enabled irq:
0000011a
mmcsd_write: startsector: 1 nsectors: 1 sectorsize: 512
mmcsd_writesingle: startblock=1
stm32_sendcmd: cmd: 0000004d arg: 00010000 regval: 0000110d enabled irq:
00000000
mmcsd_writesingle: offset=1
stm32_sendcmd: cmd: 00001458 arg: 00000001 regval: 00001158 enabled irq:
0000011a
USER MAIN:open mnt/sd0/2.txt,O_RDONLY,666
mmcsd_geometry: Entry
mmcsd_geometry: available: true mediachanged: false writeenabled: true
mmcsd_geometry: nsectors: 30535680 sectorsize: 512
mmcsd_read: startsector: 32768 nsectors: 1 sectorsize: 512
mmcsd_readsingle: startblock=32768
stm32_sendcmd: cmd: 0000004d arg: 00010000 regval: 0000110d enabled irq:
00000000
mmcsd_readsingle: offset=32768
stm32_sendcmd: cmd: 00000451 arg: 00008000 regval: 00001151 enabled irq:
0000012a
USER MAIN:open file error
```
pll config:
```
#define STM32_HSI_FREQUENCY 16000000ul
#define STM32_LSI_FREQUENCY 32000
#define STM32_HSE_FREQUENCY 8000000ul
#define STM32_LSE_FREQUENCY 32768
#define STM32_BOARD_USEHSE
#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE
#define PLL1M 4
#define PLL1N 275
#define PLL1P 1
#define PLL1Q 4
#define PLL1R 2
#define PLL2M 2
#define PLL2N 100
#define PLL2P 2
#define PLL2Q 5
#define PLL2R 8
#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \
RCC_PLLCFGR_DIVP1EN | \
RCC_PLLCFGR_DIVQ1EN)
#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(PLL1M)
#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(PLL1N)
#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(PLL1P)
#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(PLL1Q)
#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(PLL1R)
#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / PLL1M) * PLL1N)
#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / PLL1P)
#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / PLL1Q)
#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / PLL1R)
/* PLL2 */
#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \
RCC_PLLCFGR_PLL2RGE_4_8_MHZ| \
RCC_PLLCFGR_DIVQ2EN | \
RCC_PLLCFGR_DIVR2EN)
#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(PLL2M)
#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(PLL2N)
#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(PLL2P)
#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(PLL2Q)
#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(PLL2R)
#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / PLL2M) * PLL2N)
#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / PLL2P)
#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY /PLL2Q)
#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY /PLL2R)
/* PLL3 */
#define STM32_PLLCFG_PLL3CFG 0
#define STM32_PLLCFG_PLL3M 0
#define STM32_PLLCFG_PLL3N 0
#define STM32_PLLCFG_PLL3P 0
#define STM32_PLLCFG_PLL3Q 0
#define STM32_PLLCFG_PLL3R 0
#define D1CPRE_PRE 1
#define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK)
#define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY)
#define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / D1CPRE_PRE)
/* Configure Clock Assignments */
#define HPRE_PRE 2
#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK =
SYSCLK / 2 */
#define STM32_ACLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / HPRE_PRE) /*
ACLK in D1, HCLK3 in D1 */
#define STM32_HCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / HPRE_PRE) /*
HCLK in D2, HCLK4 in D3 */
#define D2PPRE1_PRE 2
#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 =
HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/D2PPRE1_PRE)
#define D2PPRE2_PRE 2
#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd2 /* PCLK2 =
HCLK / 4 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/D2PPRE2_PRE)
#define D1PPRE_PRE 2
#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd2 /* PCLK3 =
HCLK / 4 */
#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/D1PPRE_PRE)
#define D3PPRE_PRE 2
#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd2 /* PCLK4 =
HCLK / 4 */
#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/D3PPRE_PRE)
/* FLASH wait states
*
* ------------ ---------- -----------
* Vcore MAX ACLK WAIT STATES
* ------------ ---------- -----------
* 1.15-1.26 V 70 MHz 0
* (VOS1 level) 140 MHz 1
* 210 MHz 2
* 1.05-1.15 V 55 MHz 0
* (VOS2 level) 110 MHz 1
* 165 MHz 2
* 220 MHz 3
* 0.95-1.05 V 45 MHz 0
* (VOS3 level) 90 MHz 1
* 135 MHz 2
* 180 MHz 3
* 225 MHz 4
* ------------ ---------- -----------
*/
#define BOARD_FLASH_WAITSTATES 3
/* SDMMC definitions
********************************************************/
#define STM32_RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMC_PLL2
//初始化频率不能高于400K，输入频率为Pll2R=((HSE/PLL2M)*PLL2N)/PLL2R 算出来的值为50Mhz,
50M/(63*2)=396K
#define STM32_SDMMC_INIT_CLKDIV (63 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
#define STM32_SDMMC_MMCXFR_CLKDIV (3 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
//计算方法同上50M/(2*2)=12.5Mhz
#define STM32_SDMMC_SDXFR_CLKDIV (3 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
//计算方法同上50M/(2*2)=12.5Mhz
#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
```
### Verification
- [x] I have verified before submitting the report.
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