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commit 6556d4e1234f1ec72b876522821274f6c81d962c
Author: Peter van der Perk <peter.vanderp...@nxp.com>
AuthorDate: Mon May 26 09:38:24 2025 +0200

    arch/arm/imxrt: MPU reset on startup and TCM size fixes
    
    On rt10xx chips the MPU didn't got reset, which is needed for use
    with bootloaders. Furthermore the TCM sizes where fixed now we use
    kconfig symbol to set the size respectively. Also we mark ITCM as
    RO/RO so we can't change data we executed from.
---
 arch/arm/src/imxrt/imxrt_mpuinit.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.c 
b/arch/arm/src/imxrt/imxrt_mpuinit.c
index 584ef89da0..4f3ff3a2a3 100644
--- a/arch/arm/src/imxrt/imxrt_mpuinit.c
+++ b/arch/arm/src/imxrt/imxrt_mpuinit.c
@@ -270,6 +270,9 @@ void imxrt_mpu_initialize(void)
                                             * No Subregion disable       */
                        );
 #  else
+
+  mpu_reset();
+
   mpu_configure_region(0xc0000000, 512 * 1024 * 1024,
                        MPU_RASR_TEX_DEV  | /* Device
                                             * Not Cacheable
@@ -294,15 +297,15 @@ void imxrt_mpu_initialize(void)
                        MPU_RASR_AP_RORO);  /* P:RO   U:RO
                                             * Instruction access */
 
-  mpu_configure_region(IMXRT_ITCM_BASE,  128 * 1024,
+  mpu_configure_region(IMXRT_ITCM_BASE,  CONFIG_IMXRT_ITCM * 1024,
                        MPU_RASR_TEX_NOR  | /* Normal             */
                        RASR_C_VALUE      | /* Cacheable          */
                        RASR_B_VALUE      | /* Bufferable
                                             * Not Shareable      */
-                       MPU_RASR_AP_RWRW);  /* P:RW   U:RW
+                       MPU_RASR_AP_RORO);  /* P:RO   U:RO
                                             * Instruction access */
 
-  mpu_configure_region(IMXRT_DTCM_BASE,  128 * 1024,
+  mpu_configure_region(IMXRT_DTCM_BASE,  CONFIG_IMXRT_DTCM * 1024,
                        MPU_RASR_TEX_NOR  | /* Normal             */
                        RASR_C_VALUE      | /* Cacheable          */
                        RASR_B_VALUE      | /* Bufferable

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