acassis commented on a change in pull request #1491: URL: https://github.com/apache/incubator-nuttx/pull/1491#discussion_r463256160
########## File path: arch/xtensa/src/esp32/rom/esp32_spiflash.h ########## @@ -0,0 +1,823 @@ +/***************************************************************************** + * arch/xtensa/src/esp32/rom/esp32_spiflash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +#ifndef _ROM_SPI_FLASH_H_ +#define _ROM_SPI_FLASH_H_ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include <stdint.h> +#include <stdbool.h> + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** \defgroup spi_flash_apis, spi flash operation related apis + * @brief spi_flash apis + */ + +/** @addtogroup spi_flash_apis + * @{ + */ + +/***************************************************************************** + * Note + ***************************************************************************** + * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is + * used as an SPI master to access Flash and ext-SRAM by + * Cache module. It will support Decryto read for Flash, + * read/write for ext-SRAM. And SPI1 is also used as an + * SPI master for Flash read/write and ext-SRAM read/write. + * It will support Encrypto write for Flash. + * 2. As an SPI master, SPI support Highest clock to 80M, + * however, Flash with 80M Clock should be configured + * for different Flash chips. If you want to use 80M + * clock We should use the SPI that is certified by + * Espressif. However, the certification is not started + * at the time, so please use 40M clock at the moment. + * 3. SPI Flash can use 2 lines or 4 lines mode. If you + * use 2 lines mode, you can save two pad SPIHD and + * SPIWP for gpio. ESP32 support configured SPI pad for + * Flash, the configuration is stored in efuse and flash. + * However, the configurations of pads should be certified + * by Espressif. If you use this function, please use 40M + * clock at the moment. + * 4. ESP32 support to use Common SPI command to configure + * Flash to QIO mode, if you failed to configure with fix + * command. With Common SPI Command, ESP32 can also provide + * a way to use same Common SPI command groups on different + * Flash chips. + * 5. This functions are not protected by packeting, Please use the + *****************************************************************************/ + +#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 3 +#define SPI0_R_QIO_ADDR_BITSLEN 31 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 1 +#define SPI0_R_DIO_ADDR_BITSLEN 27 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 3 +#define SPI1_R_QIO_ADDR_BITSLEN 31 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 31 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B + +/* SPI address register */ + +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f + +/* SPI status register */ + +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|\ + ESP_ROM_SPIFLASH_BP1|\ + ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 + +/* Extra dummy for flash read */ + +#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 +#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1 +#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2 + +#define FLASH_ID_GD25LQ32C 0xC86016 + +typedef enum +{ + ESP_ROM_SPIFLASH_QIO_MODE = 0, + ESP_ROM_SPIFLASH_QOUT_MODE, + ESP_ROM_SPIFLASH_DIO_MODE, + ESP_ROM_SPIFLASH_DOUT_MODE, + ESP_ROM_SPIFLASH_FASTRD_MODE, + ESP_ROM_SPIFLASH_SLOWRD_MODE +} esp_rom_spiflash_read_mode_t; + +typedef enum +{ + ESP_ROM_SPIFLASH_RESULT_OK, + ESP_ROM_SPIFLASH_RESULT_ERR, + ESP_ROM_SPIFLASH_RESULT_TIMEOUT +} esp_rom_spiflash_result_t; + +typedef struct +{ + uint32_t device_id; + uint32_t chip_size; /* chip size in bytes */ + uint32_t block_size; + uint32_t sector_size; + uint32_t page_size; + uint32_t status_mask; +} esp32_spiflash_chip_t; + +typedef struct +{ + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} esp_rom_spiflash_common_cmd_t; Review comment: Thank you Greg! ---------------------------------------------------------------- This is an automated message from the Apache Git Service. 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