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lupyuen pushed a commit to branch releases/12.9
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/releases/12.9 by this push:
new f982d72766 arch/arm/sama5/spi: fix ifdelay setup in spi_setdelay call
f982d72766 is described below
commit f982d72766b6538d2d6b782dbda884cc1f68461a
Author: Michal Lenc <michall...@seznam.cz>
AuthorDate: Wed Mar 26 13:32:56 2025 +0100
arch/arm/sama5/spi: fix ifdelay setup in spi_setdelay call
ifdelay description (delay between frames) matches the DLYBCT field
(delay between consecutive transfers without removing chip select)
much better compared to stopdelay (delay between last CLK and CS
inactive). The option for stopdelay does not seem to be configurable
in SAMA5 peripheral.
Signed-off-by: Michal Lenc <michall...@seznam.cz>
---
arch/arm/src/sama5/sam_spi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c
index 48a7e6b122..327f5eebe3 100644
--- a/arch/arm/src/sama5/sam_spi.c
+++ b/arch/arm/src/sama5/sam_spi.c
@@ -1142,7 +1142,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t
startdelay,
regval |= (uint32_t) dlybs << SPI_CSR_DLYBS_SHIFT;
spi_putreg(spi, regval, offset);
- /* stopdelay = DLYBCT: Delay Between Consecutive Transfers.
+ /* ifdelay = DLYBCT: Delay Between Consecutive Transfers.
* This field defines the delay between two consecutive transfers with the
* same peripheral without removing the chip select. The delay is always
* inserted after each transfer and before removing the chip select if
@@ -1156,11 +1156,11 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t
startdelay,
*/
dlybct = SAM_SPI_CLOCK;
- dlybct *= stopdelay;
+ dlybct *= ifdelay;
dlybct /= 1000000000;
dlybct /= 32;
- if ((dlybct == 0) && (stopdelay > 0))
+ if ((dlybct == 0) && (ifdelay > 0))
{
dlybct++;
}
