pussuw commented on code in PR #15929:
URL: https://github.com/apache/nuttx/pull/15929#discussion_r1988868603
##########
arch/risc-v/src/common/riscv_mtimer.c:
##########
@@ -290,6 +377,59 @@ static int riscv_mtimer_cancel(struct oneshot_lowerhalf_s
*lower,
return 0;
}
+/****************************************************************************
+ * Name: riscv_mtimer_tick_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * lower Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ticks The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+static int riscv_mtimer_tick_cancel(struct oneshot_lowerhalf_s *lower,
+ clock_t *ticks)
+{
+ struct riscv_mtimer_lowerhalf_s *priv =
+ (struct riscv_mtimer_lowerhalf_s *)lower;
+ uint64_t mtime;
+ uint64_t alarm;
+ irqstate_t flags;
+
+ flags = up_irq_save();
+
+ alarm = priv->alarm;
+
+ mtime = riscv_mtimer_get_mtime(priv);
+
+ riscv_mtimer_set_mtimecmp(priv, mtime + UINT64_MAX);
Review Comment:
This doesn't work as you expect it to work. It will now cause the mtime
interrupt to fire immediately, as you are setting the time to current - 1.
The RISC-V mtimer keeps interrupting until mtimecmp > mtime
```
The mtime register has a 64-bit precision on all RV32, RV64, and RV128
systems. Platforms provide
a 64-bit memory-mapped machine-mode timer compare register (mtimecmp), which
causes a timer
interrupt to be posted when the mtime register contains a value greater than
or equal to the value
in the mtimecmp register. The interrupt remains posted until it is cleared
by writing the mtimecmp
register. The interrupt will only be taken if interrupts are enabled and the
MTIE bit is set in the
mie register [1].
```
[1] risc-v privileged spec 1.1, chapter 3.1.15
Machine Timer Registers (mtime and mtimecmp)
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