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The following commit(s) were added to refs/heads/master by this push:
new 9a02572e8e arch/arm/samv7/spi: fix ifdelay setup in spi_setdelay call
9a02572e8e is described below
commit 9a02572e8e38e3f6d38144b0bd8f30819dc88a53
Author: Michal Lenc <michall...@seznam.cz>
AuthorDate: Mon Feb 24 16:34:13 2025 +0100
arch/arm/samv7/spi: fix ifdelay setup in spi_setdelay call
ifdelay description (delay between frames) matches the DLYBCT field
(delay between consecutive transfers without removing chip select)
much better compared to stopdelay (delay between last CLK and CS
innactive). The option for stopdelay does not seem to be configurable
in SAMv7 peripheral.
Signed-off-by: Michal Lenc <michall...@seznam.cz>
---
arch/arm/src/samv7/sam_spi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c
index b874f5ba01..f9da85e4f7 100644
--- a/arch/arm/src/samv7/sam_spi.c
+++ b/arch/arm/src/samv7/sam_spi.c
@@ -1157,7 +1157,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t
startdelay,
regval |= (uint32_t) dlybs << SPI_CSR_DLYBS_SHIFT;
spi_putreg(spi, regval, offset);
- /* stopdelay = DLYBCT: Delay Between Consecutive Transfers.
+ /* ifdelay = DLYBCT: Delay Between Consecutive Transfers.
* This field defines the delay between two consecutive transfers with the
* same peripheral without removing the chip select. The delay is always
* inserted after each transfer and before removing the chip select if
@@ -1171,7 +1171,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t
startdelay,
*/
dlybct = SAM_SPI_CLOCK;
- dlybct *= stopdelay;
+ dlybct *= ifdelay;
dlybct /= 1000000000;
dlybct /= 32;
regval = spi_getreg(spi, offset);
