(nuttx) branch master updated: mpfs_irq.c: Interrupt claim must be cleared before disabling the source

[acassis]

This is an automated email from the ASF dual-hosted git repository.

acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new ff4d461fda mpfs_irq.c: Interrupt claim must be cleared before 
disabling the source
ff4d461fda is described below

commit ff4d461fdaed36db9e6acfe3aabb7b418b0608c2
Author: Ville Juven <ville.ju...@unikie.com>
AuthorDate: Tue Feb 18 11:14:05 2025 +0200

    mpfs_irq.c: Interrupt claim must be cleared before disabling the source
    
    From Polarfire SoC TRM:
    
    6.5.8 Interrupt Completion
    
    To signal the completion of executing an interrupt handler, the processor 
core writes the received interrupt ID to the
    Claim/Complete register. The PLIC does not check whether the completion ID 
is the same as the last claim ID for that
    target. If the completion ID does not match an interrupt source that is 
currently enabled for the target, the completion
    is ignored.
    
    The last paragraph clearly states that IRQ completion does not work for
    sources that have been disabled -> must ACK the completion before disable.
    
    Signed-off-by: Ville Juven <ville.ju...@unikie.com>
---
 arch/risc-v/src/mpfs/mpfs_irq.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/risc-v/src/mpfs/mpfs_irq.c b/arch/risc-v/src/mpfs/mpfs_irq.c
index 36b48c7d59..b9a7e4a4eb 100644
--- a/arch/risc-v/src/mpfs/mpfs_irq.c
+++ b/arch/risc-v/src/mpfs/mpfs_irq.c
@@ -133,13 +133,22 @@ void up_disable_irq(int irq)
           uintptr_t claim_address =
             mpfs_plic_get_claimbase(riscv_cpuid_to_hartid(i));
 
-          /* Clear enable bit for the irq */
+          /* Clear any already claimed IRQ (this must be done BEFORE
+           * disabling the interrupt source):
+           *
+           * To signal the completion of executing an interrupt handler, the
+           * processor core writes the received interrupt ID to the
+           * Claim/Complete register. The PLIC does not check whether the
+           * completion ID is the same as the last claim ID for that target.
+           * If the completion ID does not match an interrupt source that is
+           * currently enabled for the target, the completion is ignored.
+           */
 
-          modifyreg32(iebase + (4 * (extirq / 32)), 1 << (extirq % 32), 0);
+          putreg32(extirq, claim_address);
 
-          /* Clear any already claimed IRQ */
+          /* Clear enable bit for the irq */
 
-          putreg32(extirq, claim_address);
+          modifyreg32(iebase + (4 * (extirq / 32)), 1 << (extirq % 32), 0);
         }
     }
 }