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commit 6dbb2edd2c06993a2ef5b7d8c2127f03d1f58e74
Author: zouboan <zoub...@hotmail.com>
AuthorDate: Thu Feb 6 16:17:53 2025 +0800
Documentation:add documentation about ethernet for Zynq MPSoC and ZCU111
This commit add documentation Description for ZYNQ-MPSOC's NET driver key
features and ethernet config of ZCU111.
---
.../arm64/zynq-mpsoc/boards/zcu111/index.rst | 43 ++++++++++++++++++++++
Documentation/platforms/arm64/zynq-mpsoc/index.rst | 33 ++++++++++++++++-
2 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/Documentation/platforms/arm64/zynq-mpsoc/boards/zcu111/index.rst
b/Documentation/platforms/arm64/zynq-mpsoc/boards/zcu111/index.rst
index 797e7b90f6..b22294d3ec 100644
--- a/Documentation/platforms/arm64/zynq-mpsoc/boards/zcu111/index.rst
+++ b/Documentation/platforms/arm64/zynq-mpsoc/boards/zcu111/index.rst
@@ -60,6 +60,37 @@ LEDs and Buttons
The PS-side pushbutton SW19 is connected to MIO22 (pin U1.Y28). The PS-side
LED DS50,
which is physically placed adjacent to the pushbutton, is connected to
MIO23(pin U1.U29).
+Networking
+==========
+
+The ZCU111 board uses the TI DP83867IRPAP Ethernet RGMII PHY for Ethernet
communications
+at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII mode only. The
PHY connection
+to a user-provided Ethernet cable is through a RJ-45 connector with built-in
magnetics.
+The Ethernet connections from XCZU28DR to the DP83867 PHY device at are listed
in fllowing:
+
+=== ================== === =============
+Pin XCZU28DR Name Pin DP83867 Name
+=== ================== === =============
+J32 MIO65_ENET_TX_D0 38 TX_DO
+J34 MIO66_ENET_TX_D1 37 TX_D1
+K28 MIO67_ENET_TX_D2 36 TX_D2
+K29 MIO68_ENET_TX_D3 35 TX_D3
+K30 MIO69_ENET_TX_CTRL 52 TX_EN_TX_CTRL
+K31 MIO70_ENET_RX_CLK 43 RX_CLK
+K32 MIO71_ENET_RX_D0 44 RX_DO
+K33 MIO72_ENET_RX_D1 45 RX_D1
+K34 MIO73_ENET_RX_D2 46 RX_D2
+L29 MIO74_ENET_RX_D3 47 RX_D3
+L30 MIO75_ENET_RX_CTRL 53 RX_DV_RX_CTRL
+L33 MIO76_ENET_MDC 20 MDC
+L34 MIO77_ENET_MDIO 21 MDIO
+=== ================== === =============
+
+Networking is supported via GEM3. DHCP is not used in this configuration;
rather, a hard-coded
+IP address of 192.168.0.15 is used with a netmask of 255.255.255.0. The host
is assumed to
+be 192.168.0.101 in places. You can reconfigure to enabled DHCPC or to change
these addresses
+as you see fit.
+
Configurations
==============
@@ -83,6 +114,18 @@ zynqmp_fsbl.elf, zynqmp_pmufw.elf, bl31.elf and nuttx.elf
in Vivado SDK or XSCT
shell. Also we need copy BOOT.BIN into SD Card(in SD card boot mode) or Flash
it
into the QSPI FLASH(in QSPI boot mode).
+netjtag
+-------
+
+This is a network enabled configuration based on the NuttShell (NSH) for JTAG
boot mode
+
+netnsh
+------
+
+This is a network enabled configuration based on the NuttShell (NSH). We need
create boot
+image with zynqmp_fsbl.elf, zynqmp_pmufw.elf, bl31.elf and nuttx.elf in Vivado
SDK or XSCT
+shell. Also we need Flash BOOT.BIN intothe QSPI FLASH(in QSPI boot mode).
+
ARM64 Toolchain
===============
diff --git a/Documentation/platforms/arm64/zynq-mpsoc/index.rst
b/Documentation/platforms/arm64/zynq-mpsoc/index.rst
index e254e9eaa6..a1d31cd577 100644
--- a/Documentation/platforms/arm64/zynq-mpsoc/index.rst
+++ b/Documentation/platforms/arm64/zynq-mpsoc/index.rst
@@ -20,7 +20,7 @@ MIO Yes
EMIO Yes Depending on PL
I2C No
CAN No
-NET No
+NET Yes GEM3
SPI No
QSPI No
TIMER NO
@@ -63,6 +63,37 @@ number of interrupts which may be undesirable.
UART can be configured/operated using ``zynq_uart_*`` functions. Both receive
and
transmit can be operated in interrupt mode and polling mode.
+ETHERNET
+--------
+
+The gigabit Ethernet controller (GEM) implements a 10/100/1000 Mb/s Ethernet
MAC that
+is compatible with the IEEE Standard for Ethernet (IEEE Std 802.3-2008) and
capable of
+operating in either half or full-duplex mode in 10/100 mode and full-duplex in
1000 mode.
+The processing system (PS) is equipped with four gigabit Ethernet controllers.
Each
+controller can be configured independently. Each controller uses a reduced
gigabit media
+independent interface (RGMII) v2.0. Each GEM controller provides management
data
+input/output (MDIO) interfaces for PHY management. Key features of the NET
driver are
+summarized as follows:
+
+- Configurable MAC.
+ - Configurable DMA receive buffer size.
+ - Configurable transmit packet size.
+ - Configurable TX and RX buffer number.
+ - Preallocate or malloc TX and RX buffer.
+- Configurable PHY.
+ - MDIO phy read and write interface.
+ - Configurable phy address.
+ - PHY autonegotiation to determine speed and mode.
+ - Board support phy initialize.
+- Configurable ethernet 1,2,3,4.
+- Configurable ethernet speed 10M,100M,1000M.
+
+Access to the programmable logic (PL) is through the EMIO which provides the
gigabit
+media independent interface (GMII). Other Ethernet communications interfaces
can be
+created in the PL using the GMII available on the EMIO interface. GEM supports
the serial
+gigabit media-independent interface (SGMII, 1000BASE-SX, and 1000BASE-LX) at
1000
+Mb/s using the PS-GTR interface.
+
Psci and debug
--------------
