kywwilson11 opened a new pull request, #15718: URL: https://github.com/apache/nuttx/pull/15718
## Summary Add support for the STM32H5 ICACHE peripheral. The CortexM33 does not have typical embedded icache and dcache. Instead STM32H5 provides the ICACHE as a separate peripheral that needs to be configured. This commit adds the stm32h5 specific icache driver. The driver named functions like those in <nuttx/cache.h>. However since the CortexM33 does not have cache itself, ARCH_ICACHE is not enabled. Therefore these stm32h5 specific functions were developed. ## Impact Impacts the STM32H5 Architecture. Changes made were: 1. Kconfig - Added options for enabling the ICACHE as well as ICACHE configuration options. Configuration included enabling interrupts, setting regions, and enabling the hit/miss counters. 2. Make.defs - Build stm32_icache.c if ICACHE is configured. 3. stm32.h - Add stm32_icache.h. Reorder based on alphabet. 4. stm32_icache.h - Function declarations. 5. hardware/stm32_icache.h - Hardware register defines for ICACHE. 6. stm32_icache.c - Driver for ICACHE. Public function names emulate those in <nuttx/cache.h>. 7. stm32_start.c - Run stm32_icache_enable if ICACHE is configured. ## Testing 1. Build tests - Testing builds without warning (from cache files). 2. Cache Enabling - Testing included enabling the cache and watching hit/miss monitors. 3. Region x setup - Enabled regions in make menuconfig and confirmed registers were written properly. 4. Interrupt testing - Enabled full invalidate interrupt, made sure isr was accessed and invalidate procedure proceeded as expected. ![icache](https://github.com/user-attachments/assets/56be2bc3-e694-4a73-a756-1e19f0701c0f) -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org