no1wudi commented on code in PR #15475:
URL: https://github.com/apache/nuttx/pull/15475#discussion_r1909831239
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arch/risc-v/src/cmake/Toolchain.cmake:
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@@ -343,21 +343,19 @@ if(CONFIG_RISCV_TOOLCHAIN STREQUAL GNU_RVG)
# These models can't cover all implementation of RISCV, but it's enough for
# most cases.
- set(LLVM_CPUFLAGS)
-
if(CONFIG_ARCH_RV32)
- if(${ARCHCPUEXTFLAGS} STREQUAL imc)
- list(APPEND LLVM_CPUFLAGS -mcpu=sifive-e20)
- elseif(${ARCHCPUEXTFLAGS} STREQUAL imac)
- list(APPEND LLVM_CPUFLAGS -mcpu=sifive-e31)
- elseif(${ARCHCPUEXTFLAGS} STREQUAL imafc)
- list(APPEND LLVM_CPUFLAGS -mcpu=sifive-e76)
+ if(${ARCHCPUEXTFLAGS} MATCHES "^imc")
+ set(LLVM_CPUTYPE "sifive-e20")
Review Comment:
Because you can still pass it to compiler as `-mcpu` param in some case, it
can works although it may not be the optimal choice, it will not cause any
issues. But riscv32imc can not, it's not a valid identifier in LLVM backend:
https://github.com/apache/nuttx/blob/724797e05c8a90b9f9d170b021e403d88fc02dd3/tools/Zig.defs#L42-L46
For MCUs, symbols like sifive-e20 are merely used to indicate the ISA types
supported by the RISC-V platform and do not entail any substantive
optimizations for the CPU core itself.
For example, certain compilers using LLVM, such as wamrc, typically employ
`--cpu=generic-rv32` in conjunction with the `--cpu-features` parameter `+m,+c`
to enable support for riscv32imc. In practice, however, this is equivalent to
specifying `--cpu=sifive-e20`.
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