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new b6a4e91ef0 armv8-r/cp15: fix the problem of op1 operand confusion in
ICC_SGI1R
b6a4e91ef0 is described below
commit b6a4e91ef0e2d380ccffb041de32ab28a3a00130
Author: fanjiangang <fanjiang...@lixiang.com>
AuthorDate: Wed Oct 16 14:28:30 2024 +0800
armv8-r/cp15: fix the problem of op1 operand confusion in ICC_SGI1R
Reference:
https://developer.arm.com/documentation/100026/0103/Generic-Interrupt-Controller/GIC-programmers-model/CPU-Interface-Registers
CRn Op1 CRm Op2
ICC_SGI0R - 2 c12 -
ICC_SGI1R - 0 c12 -
Signed-off-by: fanjiangang <fanjiang...@lixiang.com>
Signed-off-by: chao an <anc...@lixiang.com>
---
arch/arm/include/armv8-r/cp15.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/armv8-r/cp15.h b/arch/arm/include/armv8-r/cp15.h
index a0c8a6c16e..0d774cf19a 100644
--- a/arch/arm/include/armv8-r/cp15.h
+++ b/arch/arm/include/armv8-r/cp15.h
@@ -173,7 +173,7 @@
#define CP15_ICC_SRE(r) _CP15(0, r, c12, c12, 5) /* ICC_SRE */
#define CP15_ICC_HSRE(r) _CP15(4, r, c12, c9, 5) /* ICC_HSRE */
#define CP15_ICC_IGRPEN1(r) _CP15(0, r, c12, c12, 7) /* ICC_IGRPEN1 */
-#define CP15_ICC_SGI1R(lo,hi) _CP15_64(2, lo, hi, c12) /* ICC_SGI1R */
+#define CP15_ICC_SGI1R(lo,hi) _CP15_64(0, lo, hi, c12) /* ICC_SGI1R */
#define CP15_SET(reg, value) \
do \
