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commit 5b14fb75bc4d863ac50933f16cfbb8da33f8d976
Author: wangming9 <wangmi...@xiaomi.com>
AuthorDate: Mon Dec 4 20:46:53 2023 +0800
arm/fpu: FPU is supported when the TEE is enabled
Summary:
1. Support armv7-a armv7-r armv8-r
2. The NSACR is read-only in Non-secure PL1 and PL2 modes.
3. The NSACR is read/write in Secure PL1 modes.
4. When the NSACR.{CP11,CP10} bit is set to 1,
Non-secure access to coprocessor 11,10 enable
Signed-off-by: wangming9 <wangmi...@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfe...@xiaomi.com>
---
arch/arm/src/armv7-a/arm_fpuconfig.S | 7 +++++++
arch/arm/src/armv7-r/arm_fpuconfig.S | 7 +++++++
arch/arm/src/armv8-r/arm_fpuconfig.S | 7 +++++++
3 files changed, 21 insertions(+)
diff --git a/arch/arm/src/armv7-a/arm_fpuconfig.S
b/arch/arm/src/armv7-a/arm_fpuconfig.S
index 52c210b422..aaa9365683 100644
--- a/arch/arm/src/armv7-a/arm_fpuconfig.S
+++ b/arch/arm/src/armv7-a/arm_fpuconfig.S
@@ -75,6 +75,13 @@ arm_fpuconfig:
mcr CP15_CPACR(r0)
/* Enable access to CP10 and CP11 in CP15.NSACR */
+
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
+ mrc CP15_NSACR(r0)
+ orr r0, r0, #0xc00
+ mcr CP15_NSACR(r0)
+#endif
+
/* REVISIT: Do we need to do this? */
/* Set FPEXC.EN (B30) */
diff --git a/arch/arm/src/armv7-r/arm_fpuconfig.S
b/arch/arm/src/armv7-r/arm_fpuconfig.S
index 5faf4631e9..6715bc762f 100644
--- a/arch/arm/src/armv7-r/arm_fpuconfig.S
+++ b/arch/arm/src/armv7-r/arm_fpuconfig.S
@@ -75,6 +75,13 @@ arm_fpuconfig:
mcr CP15_CPACR(r0)
/* Enable access to CP10 and CP11 in CP15.NSACR */
+
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
+ mrc CP15_NSACR(r0)
+ orr r0, r0, #0xc00
+ mcr CP15_NSACR(r0)
+#endif
+
/* REVISIT: Do we need to do this? */
/* Set FPEXC.EN (B30) */
diff --git a/arch/arm/src/armv8-r/arm_fpuconfig.S
b/arch/arm/src/armv8-r/arm_fpuconfig.S
index f13fc7ea4d..0cfa252514 100644
--- a/arch/arm/src/armv8-r/arm_fpuconfig.S
+++ b/arch/arm/src/armv8-r/arm_fpuconfig.S
@@ -75,6 +75,13 @@ arm_fpuconfig:
mcr CP15_CPACR(r0)
/* Enable access to CP10 and CP11 in CP15.NSACR */
+
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
+ mrc CP15_NSACR(r0)
+ orr r0, r0, #0xc00
+ mcr CP15_NSACR(r0)
+#endif
+
/* REVISIT: Do we need to do this? */
/* Set FPEXC.EN (B30) */
