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commit c00d47767118785eec1aab2433ec87229af6a489
Author: ligd <liguidi...@xiaomi.com>
AuthorDate: Wed Oct 9 21:47:43 2024 +0800
Doc: add maskable nested interrupt description
Signed-off-by: ligd <liguidi...@xiaomi.com>
---
Documentation/guides/zerolatencyinterrupts.rst | 62 ++++++++++++++++++++++++--
1 file changed, 59 insertions(+), 3 deletions(-)
diff --git a/Documentation/guides/zerolatencyinterrupts.rst
b/Documentation/guides/zerolatencyinterrupts.rst
index c44a0ce23b..bd0781f75f 100644
--- a/Documentation/guides/zerolatencyinterrupts.rst
+++ b/Documentation/guides/zerolatencyinterrupts.rst
@@ -1,6 +1,6 @@
-=========================================
-High Performance, Zero Latency Interrupts
-=========================================
+=====================================================================
+High Performance: Zero Latency Interrupts, Maskable nested interrupts
+=====================================================================
Generic Interrupt Handling
==========================
@@ -111,6 +111,62 @@ between the high priority interrupt handler and *PendSV*
interrupt
handler. A detailed discussion of that custom logic is beyond the
scope of this Wiki page.
+The following table shows the priority levels of the Cortex-M family:
+
+.. code-block::
+
+ IRQ type Priority
+ Dataabort 0x00
+ High prio IRQ1 0x20 (Zero-latency interrupt)
+ High prio IRQ2 0x30 (Can't call OS API in ISR)
+ SVC 0x70
+ Disable IRQ 0x80
+ (critical-section)
+ Low prio IRQ 0xB0
+ PendSV 0xE0
+
+As you can see, the priority levels of the zero-latency interrupts can
+beyond the critical section and SVC.
+But High prio IRQ can't call OS API.
+
+
+Maskable Nested Interrupts
+==========================
+
+The ARM Cortex-M family supports a feature called *BASEPRI* that can be
+used to disable interrupts at a priority level below a certain level.
+This feature can be used to support maskable nested interrupts.
+
+Maskable nested interrupts differ from zero-latency interrupts in
+that they obey the interrupt masking mechanisms of the system.
+For example, setting the BASEPRI register to a specific threshold will
+block all interrupts of a lower or equal priority.
+However, high-priority interrupts (such as Non-Maskable Interrupts
+or zero-latency interrupts) are unaffected by these masks.
+
+This is useful when you have a high-priority interrupt that needs to
+be able to interrupt the system, but you also have lower-priority
+interrupts that you want to be able to mask.
+
+The following table shows the priority levels of the Cortex-M family:
+
+.. code-block::
+
+ IRQ type Priority
+ Dataabort 0x00
+ SVC 0x70
+ Disable IRQ 0x80
+ (critical-section)
+ High prio IRQ1 0x90 (Maskable nested interrupt)
+ High prio IRQ2 0xA0 (Can call OS API in ISR)
+ Low prio IRQ 0xB0
+ PendSV 0xE0
+
+As you can see, the priority levels of the maskable nested interrupts
+are between the critical section and the low-priority interrupts.
+And High prio IRQ can call OS API in ISR.
+
+
Nested Interrupt Handling
=========================
