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The following commit(s) were added to refs/heads/asf-site by this push:
new 1b47d6759 Publishing web: aa582a7d73267f59d84c5725206901ad829e3351
docs: 5df3f5d4f7289142979215232d8f3d299628c7bb
1b47d6759 is described below
commit 1b47d6759d0ea8257ae4e74f480502c76a1cd43d
Author: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
AuthorDate: Thu Aug 8 00:18:43 2024 +0000
Publishing web: aa582a7d73267f59d84c5725206901ad829e3351 docs:
5df3f5d4f7289142979215232d8f3d299628c7bb
---
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content/docs/10.0.0/searchindex.js | 2 +-
content/docs/10.0.1/index.html | 2 +-
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diff --git a/content/docs/10.0.0/index.html b/content/docs/10.0.0/index.html
index 63adf515c..5c4027ead 100644
--- a/content/docs/10.0.0/index.html
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@@ -131,7 +131,7 @@ by following these <a class="reference internal"
href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation"
title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards
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standards. Additional standard APIs from Unix and other common RTOS’s (such as
VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:11</p>
+<p>Last Updated: 08 August 24 at 00:11</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
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<ul class="current">
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b/content/docs/10.0.0/searchindex.js
index d70c76280..63f92bef8 100644
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VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such as fork()).</p>
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+<p>Last Updated: 08 August 24 at 00:11</p>
<div class="toctree-wrapper compound">
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index 7dc7ef499..a85e38fe9 100644
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+<p>Last Updated: 08 August 24 at 00:11</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
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index add6259dd..af86f6ae3 100644
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-<p>Last Updated: 07 August 24 at 00:11</p>
+<p>Last Updated: 08 August 24 at 00:11</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
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<ul class="current">
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VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:12</p>
+<p>Last Updated: 08 August 24 at 00:11</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
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<ul class="current">
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b/content/docs/10.3.0/searchindex.js
index d1fc3d4fe..858ae0224 100644
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index 9f652ac6c..f4a967a62 100644
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VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:12</p>
+<p>Last Updated: 08 August 24 at 00:12</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
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<ul class="current">
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b/content/docs/11.0.0/searchindex.js
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VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:12</p>
+<p>Last Updated: 08 August 24 at 00:12</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
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<ul class="current">
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b/content/docs/12.0.0/searchindex.js
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VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:12</p>
+<p>Last Updated: 08 August 24 at 00:12</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
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<ul class="current">
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b/content/docs/12.1.0/searchindex.js
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diff --git a/content/docs/12.2.0/index.html b/content/docs/12.2.0/index.html
index 0df2ea950..dde7051a6 100644
--- a/content/docs/12.2.0/index.html
+++ b/content/docs/12.2.0/index.html
@@ -162,7 +162,7 @@ by following these <a class="reference internal"
href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation"
title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards
compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller
environments, the primary governing standards in NuttX are POSIX and ANSI
standards. Additional standard APIs from Unix and other common RTOS’s (such as
VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:12</p>
+<p>Last Updated: 08 August 24 at 00:12</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
Contents</span></p>
<ul class="current">
diff --git a/content/docs/12.2.0/searchindex.js
b/content/docs/12.2.0/searchindex.js
index eb7a66564..a4bc8e97a 100644
--- a/content/docs/12.2.0/searchindex.js
+++ b/content/docs/12.2.0/searchindex.js
@@ -1 +1 @@
-Search.setIndex({"docnames": ["applications/index",
"applications/nsh/builtin", "applications/nsh/commands",
"applications/nsh/config", "applications/nsh/customizing",
"applications/nsh/index", "applications/nsh/installation",
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"applications/nxdiag/index", "applications/wapi/commands",
"applications/wapi/index", "applications/wapi/wireless", "components/binfmt",
"components/drivers/block/index", "components/dr [...]
\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index",
"applications/nsh/builtin", "applications/nsh/commands",
"applications/nsh/config", "applications/nsh/customizing",
"applications/nsh/index", "applications/nsh/installation",
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"applications/wapi/index", "applications/wapi/wireless", "components/binfmt",
"components/drivers/block/index", "components/dr [...]
\ No newline at end of file
diff --git a/content/docs/12.2.1/index.html b/content/docs/12.2.1/index.html
index 7cbf0dedb..2a64c1272 100644
--- a/content/docs/12.2.1/index.html
+++ b/content/docs/12.2.1/index.html
@@ -162,7 +162,7 @@ by following these <a class="reference internal"
href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation"
title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards
compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller
environments, the primary governing standards in NuttX are POSIX and ANSI
standards. Additional standard APIs from Unix and other common RTOS’s (such as
VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:13</p>
+<p>Last Updated: 08 August 24 at 00:13</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
Contents</span></p>
<ul class="current">
diff --git a/content/docs/12.2.1/searchindex.js
b/content/docs/12.2.1/searchindex.js
index 33c3baef5..1c3915535 100644
--- a/content/docs/12.2.1/searchindex.js
+++ b/content/docs/12.2.1/searchindex.js
@@ -1 +1 @@
-Search.setIndex({"docnames": ["applications/index",
"applications/nsh/builtin", "applications/nsh/commands",
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"applications/wapi/index", "applications/wapi/wireless", "components/binfmt",
"components/drivers/block/index", "components/dr [...]
\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index",
"applications/nsh/builtin", "applications/nsh/commands",
"applications/nsh/config", "applications/nsh/customizing",
"applications/nsh/index", "applications/nsh/installation",
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"components/drivers/block/index", "components/dr [...]
\ No newline at end of file
diff --git a/content/docs/12.3.0/index.html b/content/docs/12.3.0/index.html
index 0298f4764..4875efe0d 100644
--- a/content/docs/12.3.0/index.html
+++ b/content/docs/12.3.0/index.html
@@ -162,7 +162,7 @@ by following these <a class="reference internal"
href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation"
title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards
compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller
environments, the primary governing standards in NuttX are POSIX and ANSI
standards. Additional standard APIs from Unix and other common RTOS’s (such as
VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:13</p>
+<p>Last Updated: 08 August 24 at 00:13</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
Contents</span></p>
<ul class="current">
diff --git a/content/docs/12.3.0/searchindex.js
b/content/docs/12.3.0/searchindex.js
index bdbe5cb54..9b3061d0c 100644
--- a/content/docs/12.3.0/searchindex.js
+++ b/content/docs/12.3.0/searchindex.js
@@ -1 +1 @@
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"applications/wapi/index", "applications/wapi/wireless", "components/binfmt",
"components/drivers/block/index", "components/dr [...]
\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index",
"applications/nsh/builtin", "applications/nsh/commands",
"applications/nsh/config", "applications/nsh/customizing",
"applications/nsh/index", "applications/nsh/installation",
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"components/drivers/block/index", "components/dr [...]
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diff --git a/content/docs/12.4.0/index.html b/content/docs/12.4.0/index.html
index 90d10a2de..642c9487e 100644
--- a/content/docs/12.4.0/index.html
+++ b/content/docs/12.4.0/index.html
@@ -169,7 +169,7 @@ standards. Additional standard APIs from Unix and other
common RTOS’s (such as
VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such
as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:13</p>
+<p>Last Updated: 08 August 24 at 00:13</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
Contents</span></p>
<ul class="current">
diff --git a/content/docs/12.4.0/searchindex.js
b/content/docs/12.4.0/searchindex.js
index 15cbe193b..2db7d9a90 100644
--- a/content/docs/12.4.0/searchindex.js
+++ b/content/docs/12.4.0/searchindex.js
@@ -1 +1 @@
-Search.setIndex({"docnames": ["applications/audioutils/fmsynt/index",
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"applications/boot/miniboot/index", "applications/canutils/candump/index",
"applications/canutils/canlib/index", "applications/canutils/cansend/index",
"applications/c [...]
\ No newline at end of file
+Search.setIndex({"docnames": ["applications/audioutils/fmsynt/index",
"applications/audioutils/index", "applications/audioutils/mml_parser/index",
"applications/audioutils/nxaudio/index",
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"applications/boot/miniboot/index", "applications/canutils/candump/index",
"applications/canutils/canlib/index", "applications/canutils/cansend/index",
"applications/c [...]
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diff --git a/content/docs/12.5.0/index.html b/content/docs/12.5.0/index.html
index 84596a766..b01d3c0f6 100644
--- a/content/docs/12.5.0/index.html
+++ b/content/docs/12.5.0/index.html
@@ -169,7 +169,7 @@ standards. Additional standard APIs from Unix and other
common RTOS’s (such as
VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such
as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:15</p>
+<p>Last Updated: 08 August 24 at 00:14</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
Contents</span></p>
<ul class="current">
diff --git a/content/docs/12.5.0/searchindex.js
b/content/docs/12.5.0/searchindex.js
index b42c3aedc..1ffdb0d3c 100644
--- a/content/docs/12.5.0/searchindex.js
+++ b/content/docs/12.5.0/searchindex.js
@@ -1 +1 @@
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"applications/boot/miniboot/index", "applications/canutils/candump/index",
"applications/canutils/canlib/index", "applications/canutils/cansend/index",
"applications/c [...]
\ No newline at end of file
+Search.setIndex({"docnames": ["applications/audioutils/fmsynt/index",
"applications/audioutils/index", "applications/audioutils/mml_parser/index",
"applications/audioutils/nxaudio/index",
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"applications/boot/miniboot/index", "applications/canutils/candump/index",
"applications/canutils/canlib/index", "applications/canutils/cansend/index",
"applications/c [...]
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diff --git a/content/docs/12.5.1/index.html b/content/docs/12.5.1/index.html
index 8c5201276..643711028 100644
--- a/content/docs/12.5.1/index.html
+++ b/content/docs/12.5.1/index.html
@@ -169,7 +169,7 @@ standards. Additional standard APIs from Unix and other
common RTOS’s (such as
VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such
as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:16</p>
+<p>Last Updated: 08 August 24 at 00:15</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
Contents</span></p>
<ul class="current">
diff --git a/content/docs/12.5.1/searchindex.js
b/content/docs/12.5.1/searchindex.js
index 40e39a18f..e9dcfed5d 100644
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"applications/canutils/canlib/index", "applications/canutils/cansend/index",
"applications/c [...]
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+Search.setIndex({"docnames": ["applications/audioutils/fmsynt/index",
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diff --git
a/content/docs/latest/_sources/components/drivers/special/i2c.rst.txt
b/content/docs/latest/_sources/components/drivers/special/i2c.rst.txt
index fa722cbf2..08d1464f3 100644
--- a/content/docs/latest/_sources/components/drivers/special/i2c.rst.txt
+++ b/content/docs/latest/_sources/components/drivers/special/i2c.rst.txt
@@ -21,3 +21,11 @@ I2C Device Drivers
- **Examples**: ``arch/z80/src/ez80/ez80_i2c.c``,
``arch/z80/src/z8/z8_i2c.c``, etc.
+
+- ``struct i2c_slaveops_s``. Each I2C slave device driver must implement
+ an instance of ``struct i2c_slaveops_s``. That structure defines a call
+ table with the following methods:
+
+- **Binding I2C Slave Drivers**. I2C slave drivers are normally directly
+ accessed by user code, We can read and write to device nodes using posix
+ interfaces.
diff --git
a/content/docs/latest/_sources/platforms/arm64/zynq-mpsoc/boards/zcu111/index.rst.txt
b/content/docs/latest/_sources/platforms/arm64/zynq-mpsoc/boards/zcu111/index.rst.txt
new file mode 100644
index 000000000..797e7b90f
--- /dev/null
+++
b/content/docs/latest/_sources/platforms/arm64/zynq-mpsoc/boards/zcu111/index.rst.txt
@@ -0,0 +1,320 @@
+=============================
+Zynq UltraScale+ RFSoC ZCU111
+=============================
+
+The `ZCU111 <https://www.xilinx.com/products/boards-and-kits/zcu111.html>`_ is
a
+development board based on the Zynq UltraScale+ RFSoC(XCZU28DR) from
XilinX(AMD).
+
+Features
+========
+
+- **RF Data Converter**
+ - **12-bit ADC:** 8, Max Rate 4.096G
+ - **14-bit DAC:** 8, Max Rate 6.554G
+ - **SD-FEC:** SD-FEC
+- **Memory**
+ - **PS DDR4:** 4GB 64-bit SODIMM
+ - **SD-Card:** Yes
+ - **M.2 SATA Connector:** Yes
+ - **QSPI:** 2
+- **Communications & Networking**
+ - **USB UART/JTAG:** 1
+ - **RJ45:** 1
+ - **SFP+:** 4
+ - **USB 3.0:** 1
+- **Expansion Connectors**
+ - **FMC-HPC Connector:** 2
+ - **PMOD:** 2
+ - **RFMC 1.0:** 2
+ - **QSPI:** 2
+- **Control & I/O**
+ - **I2C:** Yes
+ - **PMBUS:** Yes
+ - **JTAG PC4 Header:** Yes
+- **Boot Options**
+ - **ISD Boot:** Yes
+ - **QSPI Boot:** Yes
+ - **JTAG Boot:** Yes
+- **DDR4 SODIMM:** 4GB 64-bit, 2400MT/s, attached to Processor Subsystem (PS)
+
+Serial Console
+==============
+
+Serial console for the PS:
+
+===== ======== =============
+Pin Signal Notes
+===== ======== =============
+MIO18 UART0 TX USB UART COM0
+MIO19 UART0 RX USB UART COM0
+===== ======== =============
+
+PS-side UART interface and is connected to the FTDI U34 FT4232HL
USB-to-Quad-UART
+bridge port B Connect ZCU111 to our computer with the USB Cable. On our
computer
+start a Serial Terminal and connect to the USB Serial Port at **115200 bps**.
+NuttX will appear in the Serial Console when it boots on zcu111.
+
+LEDs and Buttons
+================
+
+The PS-side pushbutton SW19 is connected to MIO22 (pin U1.Y28). The PS-side
LED DS50,
+which is physically placed adjacent to the pushbutton, is connected to
MIO23(pin U1.U29).
+
+Configurations
+==============
+
+Each configuration is maintained in a sub-directory and can be selected as
follow::
+
+ tools/configure.sh zcu111:<subdir>
+
+Where <subdir> is one of the following:
+
+jtag
+----
+
+Basic NuttShell configuration for JTAG boot mode (nsh console enabled in UART0,
+UART and JTAG exposed via FT4232HL USB-to-Quad-UART bridge port and USB cable).
+
+nsh
+---
+
+Basic NuttShell configuration for Flash boot mode. We need create boot image
with
+zynqmp_fsbl.elf, zynqmp_pmufw.elf, bl31.elf and nuttx.elf in Vivado SDK or XSCT
+shell. Also we need copy BOOT.BIN into SD Card(in SD card boot mode) or Flash
it
+into the QSPI FLASH(in QSPI boot mode).
+
+ARM64 Toolchain
+===============
+
+There are two ways to install the toolchain for Zynq MPSoC:
+The first way is download the ARM64 Toolchain ``aarch64-none-elf`` from
+`Arm GNU Toolchain Downloads
<https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads>`_.
+Add the downloaded toolchain ``gcc-arm-...-aarch64-none-elf/bin``
+to the ``PATH`` Environment Variable such as:
+
+.. code-block:: console
+
+ $ echo "export
PATH=/home/username/tools/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin:$PATH"
>> ~/.profile
+
+You can edit your .profile files if you don't use bash.
+
+The second way is install Vivado SDK or Vitis development environment which
included a complete
+``aarch64-none-elf`` toolchain and we also add it to the ``PATH`` Environment
Variable such as:
+
+.. code-block:: console
+
+ $ echo "export
PATH=/home/username/tools/Xilinx/SDK/2018.3/gnu/aarch64/lin/aarch64-none/bin:$PATH"
>> ~/.profile
+
+You can edit your .profile files if you don't use bash.
+
+Note: nuttx.elf build by toolchain install in first way can't be debuged by
Vivado SDK which use
+toolchain of second way for gdb version incompatibility.
+
+Check the ARM64 Toolchain:
+
+.. code:: console
+
+ $ aarch64-none-elf-gcc -v
+
+Building
+========
+
+There are two types of NuttX image for Zynq MPSoC: debug by JTAG and boot from
FLASH.
+
+debug by jtag
+-------------
+
+We just configure the NuttX project and build the project:
+
+.. code:: console
+
+ $ cd nuttx
+ $ tools/configure.sh zcu111:jtag
+ $ make
+
+Set the Project to nuttx and Application to nuttx.elf for psu_cortexa53_0 in
Vivado SDK Debug Configuration.
+Just click Debug button then we can debug NuttX.
+
+boot from flash
+---------------
+
+To boot from FLASH, we have to create BOOT.BIN image and flash it into QSPI
FLASH or SD card. To create BOOT.BIN
+in addition to building nuttx.elf, we also need to build zynqmp_fsbl.elf,
zynqmp_pmufw.elf and bl31.elf
+To build nuttx.elf we just configure the NuttX project and build the project:
+
+.. code:: console
+
+ $ cd nuttx
+ $ tools/configure.sh zcu111:nsh
+ $ make
+
+build bl31.elf
+--------------
+
+To build bl31.elf we should fetch Fetch sources of ARM Trusted Firmware (ATF)
and checkout the tags that
+corresponding to the SDK version. Take Vivado 2018.3 for example:
+
+.. code:: console
+
+ $ git clone https://github.com/Xilinx/arm-trusted-firmware.git
+ $ cd arm-trusted-firmware
+ $ git checkout xilinx-v2018.3
+
+By default, the Arm-trusted firmware builds for OCM space at address
0xFFFEA000, and ATF assume that UBoot
+or nuttx.elf located at address 0x08000000. Then we just build bl31.elf with:
+
+.. code:: console
+
+ $ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1
+
+But, with DEBUG flag set to 1, it can't fit in OCM, so by default with
DEBUG=1, it builds for DDR location
+0x1000 with build flag DEBUG=1 mentioned while building. Alternatively, user
has always an option to build
+for the location of their choice by specifying the build flags
ZYNQMP_ATF_MEM_BASE, ZYNQMP_ATF_MEM_SIZE while
+building. The flag ZYNQMP_ATF_MEM_BASE specifies the base address of ATF and
flag ZYNQMP_ATF_MEM_SIZE specifies
+the maximum size the ATF image can be. what's more we can specifies the target
address of Uboot or nuttx.elf
+by PRELOADED_BL33_BASE. for zcu111:nsh configuration Example bl31 build
command:
+
+.. code:: console
+
+ $ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1
ZYNQMP_ATF_MEM_BASE=0x10000 ZYNQMP_ATF_MEM_SIZE=0x40000
PRELOADED_BL33_BASE=0x100000
+
+If we don't dubug bl31 we just build bl31 in following command:
+
+.. code:: console
+
+ $ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1
PRELOADED_BL33_BASE=0x100000
+
+After the build process completes the bl31.elf binary is created within the
/build/zynqmp/release/bl31 directory.
+
+build zynqmp_pmufw.elf
+----------------------
+
+The Platform Management Unit (PMU) in Zynq MPSoC has a Microblaze with 32 KB
of ROM and 128 KB of RAM. The ROM is
+pre-loaded with PMU Boot ROM (PBR) which performs pre-boot tasks and enters a
service mode. For more details on PMU,
+PBR and PMUFW load sequence, refer to Platform Management Unit (Chapter-6) in
Zynq MPSoC TRM (UG1085). PMU RAM can
+be loaded with a firmware (PMU Firmware) at run-time and can be used to extend
or customize the functionality of PMU.
+Some part of the RAM is reserved for PBR, leaving around 125.7 KB for PMU
Firmware.
+There are usually two flows to create and build a PMU Firmware image for the
target, Xilinx Vitis or Vivado SDK IDE or
+hsi command line. The PMU Firmware is provided as a template application for
the PMU processor for any hardware platform
+including the Zynq MPSoC device. The steps required to create and build it can
be applied by selecting the appropriate
+platform, processor, and template to create zynqmp_pmufw.elf. We can also
create PMU Firmware from system hardware
+project hdf file by hsi command line:
+
+.. code-block::
+
+ proc generate_pmufw {} {
+ if {[file exists pmu_fw/zynqmp_pmufw.elf] != 1} {
+ set pmufw_design [hsi::create_sw_design pmu_1 -proc psu_pmu_0 -app
zynqmp_pmufw]
+ hsi::add_library libmetal
+ hsi::generate_app -dir pmu_fw -compile
+ return "pmu_fw/zynqmp_pmufw.elf"
+ }
+ return "pmu_fw/zynqmp_pmufw.elf"
+ }
+
+In order to call this procs, the user needs to open the hdf
(hsi::open_hw_design):
+
+.. code-block::
+
+ proc create_pmufw {hdf} {
+ hsi::open_hw_design $hdf
+ set pmufw [generate_pmufw]
+ hsi::close_hw_design [hsi::current_hw_design]
+ }
+
+Create a TCL script with HSI commands above -> Create a TCL script with HSI
commands above ->
+Launch XSCT 2018.3 -> Change directory to the zipped directory -> source
xsct_script.tcl ->
+create_pmufw design_1_wrapper.hdf
+
+build zynqmp_fsbl.elf
+---------------------
+
+First Stage Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures the FPGA
with hardware bitstream (if it exists)
+and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd
Stage Boot Loader image from the non-volatile
+memory (SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes A53/R5 out of reset.
It supports multiple partitions, and each
+partition can be a code image or a bitstream. Each of these partitions, if
required, will be authenticated and/or decrypted.
+FSBL is loaded into OCM and handed off by CSU BootROM after authenticating
and/or decrypting (as required) FSBL.
+There are usually two flows to create and build a PMU Firmware image for the
target, Xilinx Vitis or Vivado SDK IDE or
+hsi command line.
+To create FSBL by Vitis or Vivado SDK IDE just launch VITIS or Vivado SDK and
do following flow:
+
+- Provide path where VITIS workspace and project need to be created. With this
VITIS workspace will be created
+- (Optional step) To work with local repos, Select "Xilinx" (ALT - x) ->
Repositories. Against Local Repositories,
+ click on "New..." and provide path of the local repo
+- Select File-->New-->Application Project to open "New Project" window,
provide name for FSBL project
+- In the “Platform” section, click on “Create a new platform from hardware
(XSA)” and select pre-defined hardware platform for ZynqMP.
+ - Alternatively, to create a new/custom platform from a .xsa file, click
on “+”, browse and select the XSA file and a new hardware platform is created.
+- In the "Domain" window, select the processor psu_cortexa53_0/psu_cortexr5_0,
OS as standalone and Language as C.
+- Click Next and select "Zynq MP FSBL"
+- Click "Finish" to generate the A53/R5 FSBL. This populates the FSBL code and
also builds it (along with BSP)
+- Debug prints in FSBL are now disabled by default. To enable debug prints,
define symbol: FSBL_DEBUG_INFO.
+ - In VITIS this can be done by: right click on FSBL application project ->
select “C/C++ Build Settings” -> “Tool Settings” tab -> Symbols (under ARM v8
gcc compiler)
+ - Click on Add (+) icon and Enter Value: FSBL_DEBUG_INFO, click on "OK" to
close the "Enter Value" screen
+- In case any of the source files (FSBL or BSP) need to be modified, browse
the file, make the change and save the file,
+ build the project. elf file will be present in the Debug/Release folder of
FSBL project.
+
+To create FSBL by XSCT command line just launch XSCT console and execute
following TCL script with HSI commands:
+
+.. code-block::
+
+ proc generate_fsbl {} {
+ if {[file exists zynqmp_fsbl/zynqmp_fsbl.elf] != 1} {
+ set fsbl_design [hsi::create_sw_design fsbl_1 -proc psu_cortexa53_0
-app zynqmp_fsbl]
+ common::set_property APP_COMPILER "aarch64-none-elf-gcc" $fsbl_design
+ common::set_property -name APP_COMPILER_FLAGS -value "-DRSA_SUPPORT
-DFSBL_DEBUG_INFO -DXPS_BOARD_ZCU111" -objects $fsbl_design
+ hsi::add_library libmetal
+ hsi::generate_app -dir zynqmp_fsbl -compile
+ }
+ return "zynqmp_fsbl/zynqmp_fsbl.elf"
+ }
+
+In order to call this procs, the user needs to open the hdf
(hsi::open_hw_design):
+
+.. code-block::
+
+ proc create_fsbl {hdf} {
+ hsi::open_hw_design $hdf
+ set fsbl [generate_fsbl]
+ hsi::close_hw_design [hsi::current_hw_design]
+ }
+
+Create a TCL script with HSI commands above -> Create a TCL script with HSI
commands above ->
+Launch XSCT 2018.3 -> Change directory to the zipped directory -> source
xsct_script.tcl ->
+create_fsbl design_1_wrapper.hdf
+
+generate BOOT.bin image
+-----------------------
+
+You can create BOOT.bin images using the BIF attributes and the Bootgen
command.
+For this configuration, the BIF file(named fsbl.bif) contains the following
attributes:
+
+.. code-block::
+
+ the_ROM_image:
+ {
+ [fsbl_config]a53_x64
+ [bootloader]zynqmp_fsbl.elf
+ [pmufw_image]zynqmp_pmufw.elf
+ [destination_cpu = a53-0, exception_level = el-3, trustzone]bl31.elf
+ [destination_cpu = a53-0, exception_level = el-1]nuttx.elf
+ }
+
+The Vitis IDE calls the following Bootgen command to generate the BOOT.bin
image for this configuration:
+
+.. code-block::
+
+ bootgen -image fsbl.bif -arch zynqmp -o .\BOOT.bin
+
+Flash BOOT.bin to QSPI FLASH
+----------------------------
+
+We can flash BOOT.bin into QSPI FLASH in following flow:
+
+- In the Vivado SDK/Vitis IDE, select Xilinx -> Program Flash.
+- In the Program Flash wizard, browse to and select the BOOT.bin image file
that was created as a part of this example.
+- Select **qspi-x8-dual_parallel** as the Flash type.
+- Set the Offset as 0 and select the BOOT.bin file.
+- Click Program to start the process of programming the QSPI flash with the
BOOT.bin.
+- Wait until you see the message “Flash Operation Successful” in the console.
+
+Set mode switch SW6 to QSPI32, NuttX will appear in the Serial Console when we
power on zcu111.
diff --git
a/content/docs/latest/_sources/platforms/arm64/zynq-mpsoc/index.rst.txt
b/content/docs/latest/_sources/platforms/arm64/zynq-mpsoc/index.rst.txt
new file mode 100644
index 000000000..e254e9eaa
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm64/zynq-mpsoc/index.rst.txt
@@ -0,0 +1,81 @@
+======================
+Zynq UltraScale+ MPSoC
+======================
+
+The Zynq UltraScale+ MPSoC family consists of a system-on-chip (SoC) style
integrated
+processing system (PS) and a Programmable Logic (PL) unit, providing an
extensible and
+flexible SoC solution on a single die.There's 64-bit Quadcore ARM Cortex-A53
Processors
+and Dualcore ARM Cortex-R5 Real-Time Processors in the MPSoC, zynq-mpsoc given
support
+for Quadcore ARM Cortex-A53 Processors of MPSoC
+
+Peripheral Support
+==================
+
+The following list indicates peripherals supported in NuttX:
+
+========== ======= ===============
+Peripheral Support Notes
+========== ======= ===============
+MIO Yes
+EMIO Yes Depending on PL
+I2C No
+CAN No
+NET No
+SPI No
+QSPI No
+TIMER NO
+UART Yes
+WDT No
+DMA No
+SDI No
+ADC No Depending on PL
+DAC No Depending on PL
+PCI NO Depending on PL
+========== ======= ===============
+
+MIO/EMIO
+--------
+
+Key features of the GPIO peripheral are summarized as follows:
+
+- 78 GPIO interfaces to the device pins.
+ - Routed through the MIO multiplexer.
+ - Programmable I/O drive strength, slew rate, and 3-state control.
+- 96 GPIO interfaces to the PL (four allocated by software to reset PL logic).
+ - Routed through the EMIO interface.
+ - Data inputs.
+ - Data outputs.
+ - Output enables.
+- I/O interface is organized into six banks (3 MIO and 3 EMIO).
+
+Pins can be configured/operated using ``zynq_mio_*`` functions. To handled 96
GPIO in 3
+EMIO banks you should map GPIO to chip's pin by HDL design in PL logic.
+
+UART
+----
+
+Zynq UltraScale+ MPSoC have two high-speed UARTs (up to 1Mb/s). The UART
controller is
+a full-duplex asynchronous receiver and transmitter that supports a wide range
of
+programmable baud rates and I/O signal formats. The controller can accommodate
+automatic parity generation and multi-master detection mode this may introduce
a large
+number of interrupts which may be undesirable.
+
+UART can be configured/operated using ``zynq_uart_*`` functions. Both receive
and
+transmit can be operated in interrupt mode and polling mode.
+
+Psci and debug
+--------------
+
+Default exception level is EL1 for the NuttX OS. However, if we debug NuttX by
JTAG
+the XSCT of Vivado SDK will set the Zynq MPSoC to EL3. so have to config NuttX
to run on
+EL3. Other levels are not supported at the moment. And in this operating
conditon
+we can't use SMC for there's no ATF support.
+
+Supported Boards
+================
+
+.. toctree::
+ :glob:
+ :maxdepth: 1
+
+ boards/*/*
diff --git a/content/docs/latest/components/drivers/special/i2c.html
b/content/docs/latest/components/drivers/special/i2c.html
index 540bed206..83c3c7cfb 100644
--- a/content/docs/latest/components/drivers/special/i2c.html
+++ b/content/docs/latest/components/drivers/special/i2c.html
@@ -237,6 +237,12 @@ higher level device driver.</p></li>
</li>
<li><p><strong>Examples</strong>: <code class="docutils literal
notranslate"><span class="pre">arch/z80/src/ez80/ez80_i2c.c</span></code>,
<code class="docutils literal notranslate"><span
class="pre">arch/z80/src/z8/z8_i2c.c</span></code>, etc.</p></li>
+<li><p><code class="docutils literal notranslate"><span
class="pre">struct</span> <span class="pre">i2c_slaveops_s</span></code>. Each
I2C slave device driver must implement
+an instance of <code class="docutils literal notranslate"><span
class="pre">struct</span> <span class="pre">i2c_slaveops_s</span></code>. That
structure defines a call
+table with the following methods:</p></li>
+<li><p><strong>Binding I2C Slave Drivers</strong>. I2C slave drivers are
normally directly
+accessed by user code, We can read and write to device nodes using posix
+interfaces.</p></li>
</ul>
</section>
diff --git a/content/docs/latest/index.html b/content/docs/latest/index.html
index 977622b92..dc628b426 100644
--- a/content/docs/latest/index.html
+++ b/content/docs/latest/index.html
@@ -170,7 +170,7 @@ standards. Additional standard APIs from Unix and other
common RTOS’s (such as
VxWorks) are adopted for functionality not available under these standards, or
for functionality that is not appropriate for deeply-embedded environments
(such
as fork()).</p>
-<p>Last Updated: 07 August 24 at 00:17</p>
+<p>Last Updated: 08 August 24 at 00:17</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of
Contents</span></p>
<ul class="current">
diff --git a/content/docs/latest/objects.inv b/content/docs/latest/objects.inv
index ffcb32b5c..44b2d02a5 100644
Binary files a/content/docs/latest/objects.inv and
b/content/docs/latest/objects.inv differ
diff --git
a/content/docs/latest/platforms/arm64/a64/boards/pinephone/index.html
b/content/docs/latest/platforms/arm64/a64/boards/pinephone/index.html
index 09df736c4..0e2fc9926 100644
--- a/content/docs/latest/platforms/arm64/a64/boards/pinephone/index.html
+++ b/content/docs/latest/platforms/arm64/a64/boards/pinephone/index.html
@@ -131,6 +131,7 @@
<li class="toctree-l3"><a class="reference internal"
href="../../../imx9/index.html">NXP i.MX9</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../../../qemu/index.html">qemu</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../../../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="../../../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../../../avr/index.html">Microchip AVR</a></li>
diff --git a/content/docs/latest/platforms/arm64/a64/index.html
b/content/docs/latest/platforms/arm64/a64/index.html
index 0646fe77d..702694621 100644
--- a/content/docs/latest/platforms/arm64/a64/index.html
+++ b/content/docs/latest/platforms/arm64/a64/index.html
@@ -131,6 +131,7 @@
<li class="toctree-l3"><a class="reference internal"
href="../imx9/index.html">NXP i.MX9</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../qemu/index.html">qemu</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../avr/index.html">Microchip AVR</a></li>
diff --git
a/content/docs/latest/platforms/arm64/fvp-v8r/boards/fvp-armv8r/index.html
b/content/docs/latest/platforms/arm64/fvp-v8r/boards/fvp-armv8r/index.html
index a469c2374..c8651b94e 100644
--- a/content/docs/latest/platforms/arm64/fvp-v8r/boards/fvp-armv8r/index.html
+++ b/content/docs/latest/platforms/arm64/fvp-v8r/boards/fvp-armv8r/index.html
@@ -131,6 +131,7 @@
<li class="toctree-l3"><a class="reference internal"
href="../../../imx9/index.html">NXP i.MX9</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../../../qemu/index.html">qemu</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../../../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="../../../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../../../avr/index.html">Microchip AVR</a></li>
diff --git a/content/docs/latest/platforms/arm64/fvp-v8r/index.html
b/content/docs/latest/platforms/arm64/fvp-v8r/index.html
index 5142e8ce7..89d958ad7 100644
--- a/content/docs/latest/platforms/arm64/fvp-v8r/index.html
+++ b/content/docs/latest/platforms/arm64/fvp-v8r/index.html
@@ -131,6 +131,7 @@
<li class="toctree-l3"><a class="reference internal"
href="../imx9/index.html">NXP i.MX9</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../qemu/index.html">qemu</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../avr/index.html">Microchip AVR</a></li>
diff --git
a/content/docs/latest/platforms/arm64/imx8/boards/imx8qm-mek/index.html
b/content/docs/latest/platforms/arm64/imx8/boards/imx8qm-mek/index.html
index f2d258a78..77fd69e72 100644
--- a/content/docs/latest/platforms/arm64/imx8/boards/imx8qm-mek/index.html
+++ b/content/docs/latest/platforms/arm64/imx8/boards/imx8qm-mek/index.html
@@ -131,6 +131,7 @@
<li class="toctree-l3"><a class="reference internal"
href="../../../imx9/index.html">NXP i.MX9</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../../../qemu/index.html">qemu</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../../../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="../../../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../../../avr/index.html">Microchip AVR</a></li>
diff --git a/content/docs/latest/platforms/arm64/imx8/index.html
b/content/docs/latest/platforms/arm64/imx8/index.html
index acb345bf8..628d6ccbe 100644
--- a/content/docs/latest/platforms/arm64/imx8/index.html
+++ b/content/docs/latest/platforms/arm64/imx8/index.html
@@ -131,6 +131,7 @@
<li class="toctree-l3"><a class="reference internal"
href="../imx9/index.html">NXP i.MX9</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../qemu/index.html">qemu</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../avr/index.html">Microchip AVR</a></li>
diff --git
a/content/docs/latest/platforms/arm64/imx9/boards/imx93-evk/index.html
b/content/docs/latest/platforms/arm64/imx9/boards/imx93-evk/index.html
index 2e4f85e98..5b0bb8c2b 100644
--- a/content/docs/latest/platforms/arm64/imx9/boards/imx93-evk/index.html
+++ b/content/docs/latest/platforms/arm64/imx9/boards/imx93-evk/index.html
@@ -131,6 +131,7 @@
</li>
<li class="toctree-l3"><a class="reference internal"
href="../../../qemu/index.html">qemu</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../../../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="../../../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../../../avr/index.html">Microchip AVR</a></li>
diff --git a/content/docs/latest/platforms/arm64/imx9/index.html
b/content/docs/latest/platforms/arm64/imx9/index.html
index d50d041e0..2a2aae4b8 100644
--- a/content/docs/latest/platforms/arm64/imx9/index.html
+++ b/content/docs/latest/platforms/arm64/imx9/index.html
@@ -131,6 +131,7 @@
</li>
<li class="toctree-l3"><a class="reference internal"
href="../qemu/index.html">qemu</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../avr/index.html">Microchip AVR</a></li>
diff --git a/content/docs/latest/platforms/arm64/index.html
b/content/docs/latest/platforms/arm64/index.html
index c28825da9..632fecca1 100644
--- a/content/docs/latest/platforms/arm64/index.html
+++ b/content/docs/latest/platforms/arm64/index.html
@@ -125,6 +125,7 @@
<li class="toctree-l3"><a class="reference internal"
href="imx9/index.html">NXP i.MX9</a></li>
<li class="toctree-l3"><a class="reference internal"
href="qemu/index.html">qemu</a></li>
<li class="toctree-l3"><a class="reference internal"
href="rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../avr/index.html">Microchip AVR</a></li>
@@ -191,6 +192,7 @@
<li class="toctree-l1"><a class="reference internal"
href="imx9/index.html">NXP i.MX9</a></li>
<li class="toctree-l1"><a class="reference internal"
href="qemu/index.html">qemu</a></li>
<li class="toctree-l1"><a class="reference internal"
href="rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l1"><a class="reference internal"
href="zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</div>
</section>
diff --git
a/content/docs/latest/platforms/arm64/qemu/boards/qemu-armv8a/index.html
b/content/docs/latest/platforms/arm64/qemu/boards/qemu-armv8a/index.html
index d4bdeb89e..93a8b2721 100644
--- a/content/docs/latest/platforms/arm64/qemu/boards/qemu-armv8a/index.html
+++ b/content/docs/latest/platforms/arm64/qemu/boards/qemu-armv8a/index.html
@@ -131,6 +131,7 @@
</ul>
</li>
<li class="toctree-l3"><a class="reference internal"
href="../../../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="../../../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../../../avr/index.html">Microchip AVR</a></li>
diff --git a/content/docs/latest/platforms/arm64/qemu/index.html
b/content/docs/latest/platforms/arm64/qemu/index.html
index 7d957d3bd..30e83e712 100644
--- a/content/docs/latest/platforms/arm64/qemu/index.html
+++ b/content/docs/latest/platforms/arm64/qemu/index.html
@@ -131,6 +131,7 @@
</ul>
</li>
<li class="toctree-l3"><a class="reference internal"
href="../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3"><a class="reference internal"
href="../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../avr/index.html">Microchip AVR</a></li>
diff --git
a/content/docs/latest/platforms/arm64/rk3399/boards/nanopi_m4/index.html
b/content/docs/latest/platforms/arm64/rk3399/boards/nanopi_m4/index.html
index 2f70b0605..a5f18c840 100644
--- a/content/docs/latest/platforms/arm64/rk3399/boards/nanopi_m4/index.html
+++ b/content/docs/latest/platforms/arm64/rk3399/boards/nanopi_m4/index.html
@@ -132,6 +132,7 @@
</li>
</ul>
</li>
+<li class="toctree-l3"><a class="reference internal"
href="../../../zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../../../avr/index.html">Microchip AVR</a></li>
diff --git
a/content/docs/latest/platforms/arm64/rk3399/boards/pinephonepro/index.html
b/content/docs/latest/platforms/arm64/rk3399/boards/pinephonepro/index.html
index 18b3c6cdc..acfcbe146 100644
--- a/content/docs/latest/platforms/arm64/rk3399/boards/pinephonepro/index.html
+++ b/content/docs/latest/platforms/arm64/rk3399/boards/pinephonepro/index.html
@@ -44,7 +44,7 @@
<script src="../../../../../_static/js/theme.js"></script>
<link rel="index" title="Index" href="../../../../../genindex.html" />
<link rel="search" title="Search" href="../../../../../search.html" />
- <link rel="next" title="Microchip AVR" href="../../../../avr/index.html" />
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+
+ <section id="zynq-ultrascale-rfsoc-zcu111">
+<h1>Zynq UltraScale+ RFSoC ZCU111<a class="headerlink"
href="#zynq-ultrascale-rfsoc-zcu111" title="Permalink to this
heading"></a></h1>
+<p>The <a class="reference external"
href="https://www.xilinx.com/products/boards-and-kits/zcu111.html";>ZCU111</a>
is a
+development board based on the Zynq UltraScale+ RFSoC(XCZU28DR) from
XilinX(AMD).</p>
+<section id="features">
+<h2>Features<a class="headerlink" href="#features" title="Permalink to this
heading"></a></h2>
+<ul class="simple">
+<li><dl class="simple">
+<dt><strong>RF Data Converter</strong></dt><dd><ul>
+<li><p><strong>12-bit ADC:</strong> 8, Max Rate 4.096G</p></li>
+<li><p><strong>14-bit DAC:</strong> 8, Max Rate 6.554G</p></li>
+<li><p><strong>SD-FEC:</strong> SD-FEC</p></li>
+</ul>
+</dd>
+</dl>
+</li>
+<li><dl class="simple">
+<dt><strong>Memory</strong></dt><dd><ul>
+<li><p><strong>PS DDR4:</strong> 4GB 64-bit SODIMM</p></li>
+<li><p><strong>SD-Card:</strong> Yes</p></li>
+<li><p><strong>M.2 SATA Connector:</strong> Yes</p></li>
+<li><p><strong>QSPI:</strong> 2</p></li>
+</ul>
+</dd>
+</dl>
+</li>
+<li><dl class="simple">
+<dt><strong>Communications & Networking</strong></dt><dd><ul>
+<li><p><strong>USB UART/JTAG:</strong> 1</p></li>
+<li><p><strong>RJ45:</strong> 1</p></li>
+<li><p><strong>SFP+:</strong> 4</p></li>
+<li><p><strong>USB 3.0:</strong> 1</p></li>
+</ul>
+</dd>
+</dl>
+</li>
+<li><dl class="simple">
+<dt><strong>Expansion Connectors</strong></dt><dd><ul>
+<li><p><strong>FMC-HPC Connector:</strong> 2</p></li>
+<li><p><strong>PMOD:</strong> 2</p></li>
+<li><p><strong>RFMC 1.0:</strong> 2</p></li>
+<li><p><strong>QSPI:</strong> 2</p></li>
+</ul>
+</dd>
+</dl>
+</li>
+<li><dl class="simple">
+<dt><strong>Control & I/O</strong></dt><dd><ul>
+<li><p><strong>I2C:</strong> Yes</p></li>
+<li><p><strong>PMBUS:</strong> Yes</p></li>
+<li><p><strong>JTAG PC4 Header:</strong> Yes</p></li>
+</ul>
+</dd>
+</dl>
+</li>
+<li><dl class="simple">
+<dt><strong>Boot Options</strong></dt><dd><ul>
+<li><p><strong>ISD Boot:</strong> Yes</p></li>
+<li><p><strong>QSPI Boot:</strong> Yes</p></li>
+<li><p><strong>JTAG Boot:</strong> Yes</p></li>
+</ul>
+</dd>
+</dl>
+</li>
+<li><p><strong>DDR4 SODIMM:</strong> 4GB 64-bit, 2400MT/s, attached to
Processor Subsystem (PS)</p></li>
+</ul>
+</section>
+<section id="serial-console">
+<h2>Serial Console<a class="headerlink" href="#serial-console"
title="Permalink to this heading"></a></h2>
+<p>Serial console for the PS:</p>
+<table class="docutils align-default">
+<thead>
+<tr class="row-odd"><th class="head"><p>Pin</p></th>
+<th class="head"><p>Signal</p></th>
+<th class="head"><p>Notes</p></th>
+</tr>
+</thead>
+<tbody>
+<tr class="row-even"><td><p>MIO18</p></td>
+<td><p>UART0 TX</p></td>
+<td><p>USB UART COM0</p></td>
+</tr>
+<tr class="row-odd"><td><p>MIO19</p></td>
+<td><p>UART0 RX</p></td>
+<td><p>USB UART COM0</p></td>
+</tr>
+</tbody>
+</table>
+<p>PS-side UART interface and is connected to the FTDI U34 FT4232HL
USB-to-Quad-UART
+bridge port B Connect ZCU111 to our computer with the USB Cable. On our
computer
+start a Serial Terminal and connect to the USB Serial Port at <strong>115200
bps</strong>.
+NuttX will appear in the Serial Console when it boots on zcu111.</p>
+</section>
+<section id="leds-and-buttons">
+<h2>LEDs and Buttons<a class="headerlink" href="#leds-and-buttons"
title="Permalink to this heading"></a></h2>
+<p>The PS-side pushbutton SW19 is connected to MIO22 (pin U1.Y28). The PS-side
LED DS50,
+which is physically placed adjacent to the pushbutton, is connected to
MIO23(pin U1.U29).</p>
+</section>
+<section id="configurations">
+<h2>Configurations<a class="headerlink" href="#configurations"
title="Permalink to this heading"></a></h2>
+<p>Each configuration is maintained in a sub-directory and can be selected as
follow:</p>
+<div class="highlight-none notranslate"><div
class="highlight"><pre><span></span>tools/configure.sh zcu111:<subdir>
+</pre></div>
+</div>
+<p>Where <subdir> is one of the following:</p>
+<section id="jtag">
+<h3>jtag<a class="headerlink" href="#jtag" title="Permalink to this
heading"></a></h3>
+<p>Basic NuttShell configuration for JTAG boot mode (nsh console enabled in
UART0,
+UART and JTAG exposed via FT4232HL USB-to-Quad-UART bridge port and USB
cable).</p>
+</section>
+<section id="nsh">
+<h3>nsh<a class="headerlink" href="#nsh" title="Permalink to this
heading"></a></h3>
+<p>Basic NuttShell configuration for Flash boot mode. We need create boot
image with
+zynqmp_fsbl.elf, zynqmp_pmufw.elf, bl31.elf and nuttx.elf in Vivado SDK or XSCT
+shell. Also we need copy BOOT.BIN into SD Card(in SD card boot mode) or Flash
it
+into the QSPI FLASH(in QSPI boot mode).</p>
+</section>
+</section>
+<section id="arm64-toolchain">
+<h2>ARM64 Toolchain<a class="headerlink" href="#arm64-toolchain"
title="Permalink to this heading"></a></h2>
+<p>There are two ways to install the toolchain for Zynq MPSoC:
+The first way is download the ARM64 Toolchain <code class="docutils literal
notranslate"><span class="pre">aarch64-none-elf</span></code> from
+<a class="reference external"
href="https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads";>Arm
GNU Toolchain Downloads</a>.
+Add the downloaded toolchain <code class="docutils literal notranslate"><span
class="pre">gcc-arm-...-aarch64-none-elf/bin</span></code>
+to the <code class="docutils literal notranslate"><span
class="pre">PATH</span></code> Environment Variable such as:</p>
+<div class="highlight-console notranslate"><div
class="highlight"><pre><span></span><span class="gp">$ </span><span
class="nb">echo</span><span class="w"> </span><span class="s2">"export
PATH=/home/username/tools/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin:</span><span
class="nv">$PATH</span><span class="s2">"</span><span class="w">
</span>>><span class="w"> </span>~/.profile
+</pre></div>
+</div>
+<p>You can edit your .profile files if you don’t use bash.</p>
+<p>The second way is install Vivado SDK or Vitis development environment which
included a complete
+<code class="docutils literal notranslate"><span
class="pre">aarch64-none-elf</span></code> toolchain and we also add it to the
<code class="docutils literal notranslate"><span class="pre">PATH</span></code>
Environment Variable such as:</p>
+<div class="highlight-console notranslate"><div
class="highlight"><pre><span></span><span class="gp">$ </span><span
class="nb">echo</span><span class="w"> </span><span class="s2">"export
PATH=/home/username/tools/Xilinx/SDK/2018.3/gnu/aarch64/lin/aarch64-none/bin:</span><span
class="nv">$PATH</span><span class="s2">"</span><span class="w">
</span>>><span class="w"> </span>~/.profile
+</pre></div>
+</div>
+<p>You can edit your .profile files if you don’t use bash.</p>
+<p>Note: nuttx.elf build by toolchain install in first way can’t be debuged by
Vivado SDK which use
+toolchain of second way for gdb version incompatibility.</p>
+<p>Check the ARM64 Toolchain:</p>
+<div class="highlight-console notranslate"><div
class="highlight"><pre><span></span><span class="gp">$
</span>aarch64-none-elf-gcc<span class="w"> </span>-v
+</pre></div>
+</div>
+</section>
+<section id="building">
+<h2>Building<a class="headerlink" href="#building" title="Permalink to this
heading"></a></h2>
+<p>There are two types of NuttX image for Zynq MPSoC: debug by JTAG and boot
from FLASH.</p>
+<section id="debug-by-jtag">
+<h3>debug by jtag<a class="headerlink" href="#debug-by-jtag" title="Permalink
to this heading"></a></h3>
+<p>We just configure the NuttX project and build the project:</p>
+<div class="highlight-console notranslate"><div
class="highlight"><pre><span></span><span class="gp">$ </span><span
class="nb">cd</span><span class="w"> </span>nuttx
+<span class="gp">$ </span>tools/configure.sh<span class="w"> </span>zcu111:jtag
+<span class="gp">$ </span>make
+</pre></div>
+</div>
+<p>Set the Project to nuttx and Application to nuttx.elf for psu_cortexa53_0
in Vivado SDK Debug Configuration.
+Just click Debug button then we can debug NuttX.</p>
+</section>
+<section id="boot-from-flash">
+<h3>boot from flash<a class="headerlink" href="#boot-from-flash"
title="Permalink to this heading"></a></h3>
+<p>To boot from FLASH, we have to create BOOT.BIN image and flash it into QSPI
FLASH or SD card. To create BOOT.BIN
+in addition to building nuttx.elf, we also need to build zynqmp_fsbl.elf,
zynqmp_pmufw.elf and bl31.elf
+To build nuttx.elf we just configure the NuttX project and build the
project:</p>
+<div class="highlight-console notranslate"><div
class="highlight"><pre><span></span><span class="gp">$ </span><span
class="nb">cd</span><span class="w"> </span>nuttx
+<span class="gp">$ </span>tools/configure.sh<span class="w"> </span>zcu111:nsh
+<span class="gp">$ </span>make
+</pre></div>
+</div>
+</section>
+<section id="build-bl31-elf">
+<h3>build bl31.elf<a class="headerlink" href="#build-bl31-elf"
title="Permalink to this heading"></a></h3>
+<p>To build bl31.elf we should fetch Fetch sources of ARM Trusted Firmware
(ATF) and checkout the tags that
+corresponding to the SDK version. Take Vivado 2018.3 for example:</p>
+<div class="highlight-console notranslate"><div
class="highlight"><pre><span></span><span class="gp">$ </span>git<span
class="w"> </span>clone<span class="w">
</span>https://github.com/Xilinx/arm-trusted-firmware.git
+<span class="gp">$ </span><span class="nb">cd</span><span class="w">
</span>arm-trusted-firmware
+<span class="gp">$ </span>git<span class="w"> </span>checkout<span class="w">
</span>xilinx-v2018.3
+</pre></div>
+</div>
+<p>By default, the Arm-trusted firmware builds for OCM space at address
0xFFFEA000, and ATF assume that UBoot
+or nuttx.elf located at address 0x08000000. Then we just build bl31.elf
with:</p>
+<div class="highlight-console notranslate"><div
class="highlight"><pre><span></span><span class="gp">$ </span>make<span
class="w"> </span><span class="nv">CROSS_COMPILE</span><span
class="o">=</span>aarch64-none-elf-<span class="w"> </span><span
class="nv">PLAT</span><span class="o">=</span>zynqmp<span class="w">
</span><span class="nv">RESET_TO_BL31</span><span class="o">=</span><span
class="m">1</span>
+</pre></div>
+</div>
+<p>But, with DEBUG flag set to 1, it can’t fit in OCM, so by default with
DEBUG=1, it builds for DDR location
+0x1000 with build flag DEBUG=1 mentioned while building. Alternatively, user
has always an option to build
+for the location of their choice by specifying the build flags
ZYNQMP_ATF_MEM_BASE, ZYNQMP_ATF_MEM_SIZE while
+building. The flag ZYNQMP_ATF_MEM_BASE specifies the base address of ATF and
flag ZYNQMP_ATF_MEM_SIZE specifies
+the maximum size the ATF image can be. what’s more we can specifies the target
address of Uboot or nuttx.elf
+by PRELOADED_BL33_BASE. for zcu111:nsh configuration Example bl31 build
command:</p>
+<div class="highlight-console notranslate"><div
class="highlight"><pre><span></span><span class="gp">$ </span>make<span
class="w"> </span><span class="nv">CROSS_COMPILE</span><span
class="o">=</span>aarch64-none-elf-<span class="w"> </span><span
class="nv">PLAT</span><span class="o">=</span>zynqmp<span class="w">
</span><span class="nv">RESET_TO_BL31</span><span class="o">=</span><span
class="m">1</span><span class="w"> </span><span
class="nv">ZYNQMP_ATF_MEM_BASE</span><span class="o">=< [...]
+</pre></div>
+</div>
+<p>If we don’t dubug bl31 we just build bl31 in following command:</p>
+<div class="highlight-console notranslate"><div
class="highlight"><pre><span></span><span class="gp">$ </span>make<span
class="w"> </span><span class="nv">CROSS_COMPILE</span><span
class="o">=</span>aarch64-none-elf-<span class="w"> </span><span
class="nv">PLAT</span><span class="o">=</span>zynqmp<span class="w">
</span><span class="nv">RESET_TO_BL31</span><span class="o">=</span><span
class="m">1</span><span class="w"> </span><span
class="nv">PRELOADED_BL33_BASE</span><span class="o">=< [...]
+</pre></div>
+</div>
+<p>After the build process completes the bl31.elf binary is created within the
/build/zynqmp/release/bl31 directory.</p>
+</section>
+<section id="build-zynqmp-pmufw-elf">
+<h3>build zynqmp_pmufw.elf<a class="headerlink" href="#build-zynqmp-pmufw-elf"
title="Permalink to this heading"></a></h3>
+<p>The Platform Management Unit (PMU) in Zynq MPSoC has a Microblaze with 32
KB of ROM and 128 KB of RAM. The ROM is
+pre-loaded with PMU Boot ROM (PBR) which performs pre-boot tasks and enters a
service mode. For more details on PMU,
+PBR and PMUFW load sequence, refer to Platform Management Unit (Chapter-6) in
Zynq MPSoC TRM (UG1085). PMU RAM can
+be loaded with a firmware (PMU Firmware) at run-time and can be used to extend
or customize the functionality of PMU.
+Some part of the RAM is reserved for PBR, leaving around 125.7 KB for PMU
Firmware.
+There are usually two flows to create and build a PMU Firmware image for the
target, Xilinx Vitis or Vivado SDK IDE or
+hsi command line. The PMU Firmware is provided as a template application for
the PMU processor for any hardware platform
+including the Zynq MPSoC device. The steps required to create and build it can
be applied by selecting the appropriate
+platform, processor, and template to create zynqmp_pmufw.elf. We can also
create PMU Firmware from system hardware
+project hdf file by hsi command line:</p>
+<div class="highlight-none notranslate"><div
class="highlight"><pre><span></span>proc generate_pmufw {} {
+ if {[file exists pmu_fw/zynqmp_pmufw.elf] != 1} {
+ set pmufw_design [hsi::create_sw_design pmu_1 -proc psu_pmu_0 -app
zynqmp_pmufw]
+ hsi::add_library libmetal
+ hsi::generate_app -dir pmu_fw -compile
+ return "pmu_fw/zynqmp_pmufw.elf"
+ }
+ return "pmu_fw/zynqmp_pmufw.elf"
+}
+</pre></div>
+</div>
+<p>In order to call this procs, the user needs to open the hdf
(hsi::open_hw_design):</p>
+<div class="highlight-none notranslate"><div
class="highlight"><pre><span></span>proc create_pmufw {hdf} {
+ hsi::open_hw_design $hdf
+ set pmufw [generate_pmufw]
+ hsi::close_hw_design [hsi::current_hw_design]
+}
+</pre></div>
+</div>
+<p>Create a TCL script with HSI commands above -> Create a TCL script with
HSI commands above ->
+Launch XSCT 2018.3 -> Change directory to the zipped directory -> source
xsct_script.tcl ->
+create_pmufw design_1_wrapper.hdf</p>
+</section>
+<section id="build-zynqmp-fsbl-elf">
+<h3>build zynqmp_fsbl.elf<a class="headerlink" href="#build-zynqmp-fsbl-elf"
title="Permalink to this heading"></a></h3>
+<p>First Stage Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures the
FPGA with hardware bitstream (if it exists)
+and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd
Stage Boot Loader image from the non-volatile
+memory (SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes A53/R5 out of reset.
It supports multiple partitions, and each
+partition can be a code image or a bitstream. Each of these partitions, if
required, will be authenticated and/or decrypted.
+FSBL is loaded into OCM and handed off by CSU BootROM after authenticating
and/or decrypting (as required) FSBL.
+There are usually two flows to create and build a PMU Firmware image for the
target, Xilinx Vitis or Vivado SDK IDE or
+hsi command line.
+To create FSBL by Vitis or Vivado SDK IDE just launch VITIS or Vivado SDK and
do following flow:</p>
+<ul class="simple">
+<li><p>Provide path where VITIS workspace and project need to be created. With
this VITIS workspace will be created</p></li>
+<li><p>(Optional step) To work with local repos, Select “Xilinx” (ALT - x)
-> Repositories. Against Local Repositories,
+click on “New…” and provide path of the local repo</p></li>
+<li><p>Select File–>New–>Application Project to open “New Project”
window, provide name for FSBL project</p></li>
+<li><dl class="simple">
+<dt>In the “Platform” section, click on “Create a new platform from hardware
(XSA)” and select pre-defined hardware platform for ZynqMP.</dt><dd><ul>
+<li><p>Alternatively, to create a new/custom platform from a .xsa file, click
on “+”, browse and select the XSA file and a new hardware platform is
created.</p></li>
+</ul>
+</dd>
+</dl>
+</li>
+<li><p>In the “Domain” window, select the processor
psu_cortexa53_0/psu_cortexr5_0, OS as standalone and Language as C.</p></li>
+<li><p>Click Next and select “Zynq MP FSBL”</p></li>
+<li><p>Click “Finish” to generate the A53/R5 FSBL. This populates the FSBL
code and also builds it (along with BSP)</p></li>
+<li><dl class="simple">
+<dt>Debug prints in FSBL are now disabled by default. To enable debug prints,
define symbol: FSBL_DEBUG_INFO.</dt><dd><ul>
+<li><p>In VITIS this can be done by: right click on FSBL application project
-> select “C/C++ Build Settings” -> “Tool Settings” tab -> Symbols
(under ARM v8 gcc compiler)</p></li>
+<li><p>Click on Add (+) icon and Enter Value: FSBL_DEBUG_INFO, click on “OK”
to close the “Enter Value” screen</p></li>
+</ul>
+</dd>
+</dl>
+</li>
+<li><p>In case any of the source files (FSBL or BSP) need to be modified,
browse the file, make the change and save the file,
+build the project. elf file will be present in the Debug/Release folder of
FSBL project.</p></li>
+</ul>
+<p>To create FSBL by XSCT command line just launch XSCT console and execute
following TCL script with HSI commands:</p>
+<div class="highlight-none notranslate"><div
class="highlight"><pre><span></span>proc generate_fsbl {} {
+ if {[file exists zynqmp_fsbl/zynqmp_fsbl.elf] != 1} {
+ set fsbl_design [hsi::create_sw_design fsbl_1 -proc psu_cortexa53_0
-app zynqmp_fsbl]
+ common::set_property APP_COMPILER "aarch64-none-elf-gcc"
$fsbl_design
+ common::set_property -name APP_COMPILER_FLAGS -value
"-DRSA_SUPPORT -DFSBL_DEBUG_INFO -DXPS_BOARD_ZCU111" -objects
$fsbl_design
+ hsi::add_library libmetal
+ hsi::generate_app -dir zynqmp_fsbl -compile
+ }
+ return "zynqmp_fsbl/zynqmp_fsbl.elf"
+}
+</pre></div>
+</div>
+<p>In order to call this procs, the user needs to open the hdf
(hsi::open_hw_design):</p>
+<div class="highlight-none notranslate"><div
class="highlight"><pre><span></span>proc create_fsbl {hdf} {
+ hsi::open_hw_design $hdf
+ set fsbl [generate_fsbl]
+ hsi::close_hw_design [hsi::current_hw_design]
+}
+</pre></div>
+</div>
+<p>Create a TCL script with HSI commands above -> Create a TCL script with
HSI commands above ->
+Launch XSCT 2018.3 -> Change directory to the zipped directory -> source
xsct_script.tcl ->
+create_fsbl design_1_wrapper.hdf</p>
+</section>
+<section id="generate-boot-bin-image">
+<h3>generate BOOT.bin image<a class="headerlink"
href="#generate-boot-bin-image" title="Permalink to this heading"></a></h3>
+<p>You can create BOOT.bin images using the BIF attributes and the Bootgen
command.
+For this configuration, the BIF file(named fsbl.bif) contains the following
attributes:</p>
+<div class="highlight-none notranslate"><div
class="highlight"><pre><span></span>the_ROM_image:
+{
+ [fsbl_config]a53_x64
+ [bootloader]zynqmp_fsbl.elf
+ [pmufw_image]zynqmp_pmufw.elf
+ [destination_cpu = a53-0, exception_level = el-3, trustzone]bl31.elf
+ [destination_cpu = a53-0, exception_level = el-1]nuttx.elf
+}
+</pre></div>
+</div>
+<p>The Vitis IDE calls the following Bootgen command to generate the BOOT.bin
image for this configuration:</p>
+<div class="highlight-none notranslate"><div
class="highlight"><pre><span></span>bootgen -image fsbl.bif -arch zynqmp -o
.\BOOT.bin
+</pre></div>
+</div>
+</section>
+<section id="flash-boot-bin-to-qspi-flash">
+<h3>Flash BOOT.bin to QSPI FLASH<a class="headerlink"
href="#flash-boot-bin-to-qspi-flash" title="Permalink to this
heading"></a></h3>
+<p>We can flash BOOT.bin into QSPI FLASH in following flow:</p>
+<ul class="simple">
+<li><p>In the Vivado SDK/Vitis IDE, select Xilinx -> Program Flash.</p></li>
+<li><p>In the Program Flash wizard, browse to and select the BOOT.bin image
file that was created as a part of this example.</p></li>
+<li><p>Select <strong>qspi-x8-dual_parallel</strong> as the Flash
type.</p></li>
+<li><p>Set the Offset as 0 and select the BOOT.bin file.</p></li>
+<li><p>Click Program to start the process of programming the QSPI flash with
the BOOT.bin.</p></li>
+<li><p>Wait until you see the message “Flash Operation Successful” in the
console.</p></li>
+</ul>
+<p>Set mode switch SW6 to QSPI32, NuttX will appear in the Serial Console when
we power on zcu111.</p>
+</section>
+</section>
+</section>
+
+
+ </div>
+ </div>
+ <footer><div class="rst-footer-buttons" role="navigation"
aria-label="Footer">
+ <a href="../../index.html" class="btn btn-neutral float-left"
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+ <a href="../../../../avr/index.html" class="btn btn-neutral
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+ </div>
+
+ <hr/>
+
+ <div role="contentinfo">
+ <p>© Copyright 2023, The Apache Software Foundation.</p>
+ </div>
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+
+</footer>
+ </div>
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diff --git a/content/docs/latest/platforms/arm64/a64/index.html
b/content/docs/latest/platforms/arm64/zynq-mpsoc/index.html
similarity index 63%
copy from content/docs/latest/platforms/arm64/a64/index.html
copy to content/docs/latest/platforms/arm64/zynq-mpsoc/index.html
index 0646fe77d..941b17506 100644
--- a/content/docs/latest/platforms/arm64/a64/index.html
+++ b/content/docs/latest/platforms/arm64/zynq-mpsoc/index.html
@@ -23,7 +23,7 @@
<meta charset="utf-8" /><meta name="generator" content="Docutils 0.18.1:
http://docutils.sourceforge.net/"; />
<meta name="viewport" content="width=device-width, initial-scale=1.0" />
- <title>Allwinner A64 — NuttX latest documentation</title>
+ <title>Zynq UltraScale+ MPSoC — NuttX latest documentation</title>
<link rel="stylesheet" href="../../../_static/pygments.css"
type="text/css" />
<link rel="stylesheet" href="../../../_static/css/theme.css"
type="text/css" />
<link rel="stylesheet" href="../../../_static/copybutton.css"
type="text/css" />
@@ -44,8 +44,8 @@
<script src="../../../_static/js/theme.js"></script>
<link rel="index" title="Index" href="../../../genindex.html" />
<link rel="search" title="Search" href="../../../search.html" />
- <link rel="next" title="PINE64 PinePhone"
href="boards/pinephone/index.html" />
- <link rel="prev" title="ARM64" href="../index.html" />
+ <link rel="next" title="Zynq UltraScale+ RFSoC ZCU111"
href="boards/zcu111/index.html" />
+ <link rel="prev" title="pinephonepro"
href="../rk3399/boards/pinephonepro/index.html" />
</head>
<body class="wy-body-for-nav">
@@ -119,18 +119,25 @@
<li class="toctree-l1 current"><a class="reference internal"
href="../../index.html">Supported Platforms</a><ul class="current">
<li class="toctree-l2"><a class="reference internal"
href="../../arm/index.html">ARM</a></li>
<li class="toctree-l2 current"><a class="reference internal"
href="../index.html">ARM64</a><ul class="current">
-<li class="toctree-l3 current"><a class="current reference internal"
href="#">Allwinner A64</a><ul>
-<li class="toctree-l4"><a class="reference internal"
href="#supported-boards">Supported Boards</a><ul>
-<li class="toctree-l5"><a class="reference internal"
href="boards/pinephone/index.html">PINE64 PinePhone</a></li>
-</ul>
-</li>
-</ul>
-</li>
+<li class="toctree-l3"><a class="reference internal"
href="../a64/index.html">Allwinner A64</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../fvp-v8r/index.html">fvp-v8r</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../imx8/index.html">NXP i.MX8</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../imx9/index.html">NXP i.MX9</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../qemu/index.html">qemu</a></li>
<li class="toctree-l3"><a class="reference internal"
href="../rk3399/index.html">Rockchip rk3399</a></li>
+<li class="toctree-l3 current"><a class="current reference internal"
href="#">Zynq UltraScale+ MPSoC</a><ul>
+<li class="toctree-l4"><a class="reference internal"
href="#peripheral-support">Peripheral Support</a><ul>
+<li class="toctree-l5"><a class="reference internal"
href="#mio-emio">MIO/EMIO</a></li>
+<li class="toctree-l5"><a class="reference internal" href="#uart">UART</a></li>
+<li class="toctree-l5"><a class="reference internal"
href="#psci-and-debug">Psci and debug</a></li>
+</ul>
+</li>
+<li class="toctree-l4"><a class="reference internal"
href="#supported-boards">Supported Boards</a><ul>
+<li class="toctree-l5"><a class="reference internal"
href="boards/zcu111/index.html">Zynq UltraScale+ RFSoC ZCU111</a></li>
+</ul>
+</li>
+</ul>
+</li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal"
href="../../avr/index.html">Microchip AVR</a></li>
@@ -177,9 +184,9 @@
<li><a href="../../../index.html" class="icon icon-home"
aria-label="Home"></a></li>
<li class="breadcrumb-item"><a href="../../index.html">Supported
Platforms</a></li>
<li class="breadcrumb-item"><a href="../index.html">ARM64</a></li>
- <li class="breadcrumb-item active">Allwinner A64</li>
+ <li class="breadcrumb-item active">Zynq UltraScale+ MPSoC</li>
<li class="wy-breadcrumbs-aside">
- <a href="../../../_sources/platforms/arm64/a64/index.rst.txt"
rel="nofollow"> View page source</a>
+ <a
href="../../../_sources/platforms/arm64/zynq-mpsoc/index.rst.txt"
rel="nofollow"> View page source</a>
</li>
</ul>
<hr/>
@@ -187,20 +194,136 @@
<div role="main" class="document" itemscope="itemscope"
itemtype="http://schema.org/Article";>
<div itemprop="articleBody">
- <section id="allwinner-a64">
-<h1>Allwinner A64<a class="headerlink" href="#allwinner-a64" title="Permalink
to this heading"></a></h1>
-<p><a class="reference external" href="https://linux-sunxi.org/A64";>Allwinner
A64</a> is an ARM64 SoC that features:</p>
+ <section id="zynq-ultrascale-mpsoc">
+<h1>Zynq UltraScale+ MPSoC<a class="headerlink" href="#zynq-ultrascale-mpsoc"
title="Permalink to this heading"></a></h1>
+<p>The Zynq UltraScale+ MPSoC family consists of a system-on-chip (SoC) style
integrated
+processing system (PS) and a Programmable Logic (PL) unit, providing an
extensible and
+flexible SoC solution on a single die.There’s 64-bit Quadcore ARM Cortex-A53
Processors
+and Dualcore ARM Cortex-R5 Real-Time Processors in the MPSoC, zynq-mpsoc given
support
+for Quadcore ARM Cortex-A53 Processors of MPSoC</p>
+<section id="peripheral-support">
+<h2>Peripheral Support<a class="headerlink" href="#peripheral-support"
title="Permalink to this heading"></a></h2>
+<p>The following list indicates peripherals supported in NuttX:</p>
+<table class="docutils align-default">
+<thead>
+<tr class="row-odd"><th class="head"><p>Peripheral</p></th>
+<th class="head"><p>Support</p></th>
+<th class="head"><p>Notes</p></th>
+</tr>
+</thead>
+<tbody>
+<tr class="row-even"><td><p>MIO</p></td>
+<td><p>Yes</p></td>
+<td></td>
+</tr>
+<tr class="row-odd"><td><p>EMIO</p></td>
+<td><p>Yes</p></td>
+<td><p>Depending on PL</p></td>
+</tr>
+<tr class="row-even"><td><p>I2C</p></td>
+<td><p>No</p></td>
+<td></td>
+</tr>
+<tr class="row-odd"><td><p>CAN</p></td>
+<td><p>No</p></td>
+<td></td>
+</tr>
+<tr class="row-even"><td><p>NET</p></td>
+<td><p>No</p></td>
+<td></td>
+</tr>
+<tr class="row-odd"><td><p>SPI</p></td>
+<td><p>No</p></td>
+<td></td>
+</tr>
+<tr class="row-even"><td><p>QSPI</p></td>
+<td><p>No</p></td>
+<td></td>
+</tr>
+<tr class="row-odd"><td><p>TIMER</p></td>
+<td><p>NO</p></td>
+<td></td>
+</tr>
+<tr class="row-even"><td><p>UART</p></td>
+<td><p>Yes</p></td>
+<td></td>
+</tr>
+<tr class="row-odd"><td><p>WDT</p></td>
+<td><p>No</p></td>
+<td></td>
+</tr>
+<tr class="row-even"><td><p>DMA</p></td>
+<td><p>No</p></td>
+<td></td>
+</tr>
+<tr class="row-odd"><td><p>SDI</p></td>
+<td><p>No</p></td>
+<td></td>
+</tr>
+<tr class="row-even"><td><p>ADC</p></td>
+<td><p>No</p></td>
+<td><p>Depending on PL</p></td>
+</tr>
+<tr class="row-odd"><td><p>DAC</p></td>
+<td><p>No</p></td>
+<td><p>Depending on PL</p></td>
+</tr>
+<tr class="row-even"><td><p>PCI</p></td>
+<td><p>NO</p></td>
+<td><p>Depending on PL</p></td>
+</tr>
+</tbody>
+</table>
+<section id="mio-emio">
+<h3>MIO/EMIO<a class="headerlink" href="#mio-emio" title="Permalink to this
heading"></a></h3>
+<p>Key features of the GPIO peripheral are summarized as follows:</p>
<ul class="simple">
-<li><p><strong>CPU:</strong> Quad-Core ARM Cortex-A53</p></li>
-<li><p><strong>GPU:</strong> ARM Mali400 MP2</p></li>
-<li><p><strong>Interrupt Controller:</strong> ARM GIC PL400 (Generic Interrupt
Controller v2)</p></li>
-<li><p><strong>Display Engine:</strong> Allwinner Display Engine 2.0 (MIPI DSI
with DMA)</p></li>
+<li><dl class="simple">
+<dt>78 GPIO interfaces to the device pins.</dt><dd><ul>
+<li><p>Routed through the MIO multiplexer.</p></li>
+<li><p>Programmable I/O drive strength, slew rate, and 3-state
control.</p></li>
+</ul>
+</dd>
+</dl>
+</li>
+<li><dl class="simple">
+<dt>96 GPIO interfaces to the PL (four allocated by software to reset PL
logic).</dt><dd><ul>
+<li><p>Routed through the EMIO interface.</p></li>
+<li><p>Data inputs.</p></li>
+<li><p>Data outputs.</p></li>
+<li><p>Output enables.</p></li>
+</ul>
+</dd>
+</dl>
+</li>
+<li><p>I/O interface is organized into six banks (3 MIO and 3 EMIO).</p></li>
</ul>
+<p>Pins can be configured/operated using <code class="docutils literal
notranslate"><span class="pre">zynq_mio_*</span></code> functions. To handled
96 GPIO in 3
+EMIO banks you should map GPIO to chip’s pin by HDL design in PL logic.</p>
+</section>
+<section id="uart">
+<h3>UART<a class="headerlink" href="#uart" title="Permalink to this
heading"></a></h3>
+<p>Zynq UltraScale+ MPSoC have two high-speed UARTs (up to 1Mb/s). The UART
controller is
+a full-duplex asynchronous receiver and transmitter that supports a wide range
of
+programmable baud rates and I/O signal formats. The controller can accommodate
+automatic parity generation and multi-master detection mode this may introduce
a large
+number of interrupts which may be undesirable.</p>
+<p>UART can be configured/operated using <code class="docutils literal
notranslate"><span class="pre">zynq_uart_*</span></code> functions. Both
receive and
+transmit can be operated in interrupt mode and polling mode.</p>
+</section>
+<section id="psci-and-debug">
+<h3>Psci and debug<a class="headerlink" href="#psci-and-debug"
title="Permalink to this heading"></a></h3>
+<p>Default exception level is EL1 for the NuttX OS. However, if we debug NuttX
by JTAG
+the XSCT of Vivado SDK will set the Zynq MPSoC to EL3. so have to config NuttX
to run on
+EL3. Other levels are not supported at the moment. And in this operating
conditon
+we can’t use SMC for there’s no ATF support.</p>
+</section>
+</section>
<section id="supported-boards">
<h2>Supported Boards<a class="headerlink" href="#supported-boards"
title="Permalink to this heading"></a></h2>
<div class="toctree-wrapper compound">
<ul>
-<li class="toctree-l1"><a class="reference internal"
href="boards/pinephone/index.html">PINE64 PinePhone</a></li>
+<li class="toctree-l1"><a class="reference internal"
href="boards/zcu111/index.html">Zynq UltraScale+ RFSoC ZCU111</a></li>
</ul>
</div>
</section>
@@ -210,8 +333,8 @@
</div>
</div>
<footer><div class="rst-footer-buttons" role="navigation"
aria-label="Footer">
- <a href="../index.html" class="btn btn-neutral float-left"
title="ARM64" accesskey="p" rel="prev"><span class="fa fa-arrow-circle-left"
aria-hidden="true"></span> Previous</a>
- <a href="boards/pinephone/index.html" class="btn btn-neutral
float-right" title="PINE64 PinePhone" accesskey="n" rel="next">Next <span
class="fa fa-arrow-circle-right" aria-hidden="true"></span></a>
+ <a href="../rk3399/boards/pinephonepro/index.html" class="btn
btn-neutral float-left" title="pinephonepro" accesskey="p" rel="prev"><span
class="fa fa-arrow-circle-left" aria-hidden="true"></span> Previous</a>
+ <a href="boards/zcu111/index.html" class="btn btn-neutral float-right"
title="Zynq UltraScale+ RFSoC ZCU111" accesskey="n" rel="next">Next <span
class="fa fa-arrow-circle-right" aria-hidden="true"></span></a>
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<hr/>
diff --git a/content/docs/latest/platforms/avr/index.html
b/content/docs/latest/platforms/avr/index.html
index 4954df90d..0d24fa56a 100644
--- a/content/docs/latest/platforms/avr/index.html
+++ b/content/docs/latest/platforms/avr/index.html
@@ -45,7 +45,7 @@
<link rel="index" title="Index" href="../../genindex.html" />
<link rel="search" title="Search" href="../../search.html" />
<link rel="next" title="Microchip AT32UC3" href="at32uc3/index.html" />
- <link rel="prev" title="pinephonepro"
href="../arm64/rk3399/boards/pinephonepro/index.html" />
+ <link rel="prev" title="Zynq UltraScale+ RFSoC ZCU111"
href="../arm64/zynq-mpsoc/boards/zcu111/index.html" />
</head>
<body class="wy-body-for-nav">
@@ -193,7 +193,7 @@
</div>
</div>
<footer><div class="rst-footer-buttons" role="navigation"
aria-label="Footer">
- <a href="../arm64/rk3399/boards/pinephonepro/index.html" class="btn
btn-neutral float-left" title="pinephonepro" accesskey="p" rel="prev"><span
class="fa fa-arrow-circle-left" aria-hidden="true"></span> Previous</a>
+ <a href="../arm64/zynq-mpsoc/boards/zcu111/index.html" class="btn
btn-neutral float-left" title="Zynq UltraScale+ RFSoC ZCU111" accesskey="p"
rel="prev"><span class="fa fa-arrow-circle-left" aria-hidden="true"></span>
Previous</a>
<a href="at32uc3/index.html" class="btn btn-neutral float-right"
title="Microchip AT32UC3" accesskey="n" rel="next">Next <span class="fa
fa-arrow-circle-right" aria-hidden="true"></span></a>
</div>
diff --git a/content/docs/latest/platforms/index.html
b/content/docs/latest/platforms/index.html
index 35a4899b9..e62b2a334 100644
--- a/content/docs/latest/platforms/index.html
+++ b/content/docs/latest/platforms/index.html
@@ -591,6 +591,10 @@ series and boards supported in NuttX:</p>
<li class="toctree-l3"><a class="reference internal"
href="arm64/rk3399/boards/pinephonepro/index.html">pinephonepro</a></li>
</ul>
</li>
+<li class="toctree-l2"><a class="reference internal"
href="arm64/zynq-mpsoc/index.html">Zynq UltraScale+ MPSoC</a><ul>
+<li class="toctree-l3"><a class="reference internal"
href="arm64/zynq-mpsoc/boards/zcu111/index.html">Zynq UltraScale+ RFSoC
ZCU111</a></li>
+</ul>
+</li>
</ul>
</li>
<li class="toctree-l1"><a class="reference internal"
href="avr/index.html">Microchip AVR</a><ul>
diff --git a/content/docs/latest/searchindex.js
b/content/docs/latest/searchindex.js
index 7277de374..382c3ac96 100644
--- a/content/docs/latest/searchindex.js
+++ b/content/docs/latest/searchindex.js
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"applications/benchmarks/dhrystone/index", "applications/benchmarks/fio/index",
"applications/benchmarks/index", "applications/benchmarks/iozone/index",
"applications/bench [...]
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+Search.setIndex({"docnames": ["applications/audioutils/fmsynt/index",
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index aa60c8851..e1025c183 100644
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