no1wudi commented on code in PR #12554: URL: https://github.com/apache/nuttx/pull/12554#discussion_r1671692775
########## arch/risc-v/include/qemu-rv/chip.h: ########## @@ -21,4 +21,14 @@ #ifndef __ARCH_RISCV_INCLUDE_QEMU_RV_CHIP_H #define __ARCH_RISCV_INCLUDE_QEMU_RV_CHIP_H +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Refer to https://github.com/qemu/qemu/blob/master/target/riscv/debug.c + * for the definition of the following macros. + */ + +#define RISCV_DEBUG_NR_TRIGGER 2 Review Comment: It's easy to get from reference manual, and only need to be configured once for each SoC, similar to NR_IRQ. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
