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new 3e85c1886e esp32/dac-one-shot: lower-half driver for ESP32 internal DAC
3e85c1886e is described below
commit 3e85c1886e61dad56e9abc1ae42fc437d9411b86
Author: Tomáš Pilný <tomas.pi...@espressif.com>
AuthorDate: Tue Nov 28 15:50:59 2023 +0100
esp32/dac-one-shot: lower-half driver for ESP32 internal DAC
Enable with ./tools/configure.sh -l esp32-devkitc:dac
DAC channel 0 = GPIO 25
DAC channel 1 = GPIO 26
default path: /dev/dac0
Resolution 8 bits = values 0~255
Voltage: 0~Vref
The reference voltage 'Vref' here is input from the pin VDD3P3_RTC
which ideally equals to the power supply VDD (3.3V).
---
.../xtensa/esp32/boards/esp32-devkitc/index.rst | 27 +
Documentation/platforms/xtensa/esp32/index.rst | 1 +
arch/xtensa/src/esp32/Kconfig | 29 +
arch/xtensa/src/esp32/Make.defs | 4 +
arch/xtensa/src/esp32/esp32_dac.c | 399 ++++++
arch/xtensa/src/esp32/esp32_dac.h | 65 +
arch/xtensa/src/esp32/hardware/esp32_sens.h | 1281 +++++++++++++++-----
.../xtensa/esp32/common/include/esp32_board_dac.h | 84 ++
boards/xtensa/esp32/common/src/Make.defs | 4 +
boards/xtensa/esp32/common/src/esp32_board_dac.c | 79 ++
.../esp32/esp32-devkitc/configs/dac/defconfig | 48 +
.../xtensa/esp32/esp32-devkitc/src/esp32_bringup.c | 12 +
12 files changed, 1761 insertions(+), 272 deletions(-)
diff --git
a/Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst
b/Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst
index d346d8ce84..64086aa3e7 100644
--- a/Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst
+++ b/Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst
@@ -329,6 +329,33 @@ was successful by running ``cxxtest``::
Invalid file! /invalid
File /proc/version exists!
+dac
+---
+This configuration enables DAC and registers a `DAC example application
<https://github.com/apache/nuttx-apps/tree/master/examples/dac>`_.
+
+.. note:: The DAC module is hard-wired to pins 25 (channel 0) and 26
+ (channel 1). The default device name is ``/dev/dac0`` and can be changed in
+ the config menu.
+
+.. note:: The DAC channels in `IDF
<https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/dac.html>`_
are numbered ``channel 1`` (pin 25) and ``channel 2`` (pin 26).
+
+.. note:: Max value 255 should be close to VRef (3.3V) but it probably will
not.
+ You can more realistically expect to get voltage around 3.09V.
+
+With this example you can use (not only) the following commands:
+
+For a multimeter, you can use the command:
+
+``dac -d 5000 -s 32 test``
+
+For oscilloscope or anything else with tracing:
+
+``dac -d 0 -s 4 test``
+
+For more info about the example capabilities invoke help message by typing
+
+``dac -h``
+
efuse
-----
diff --git a/Documentation/platforms/xtensa/esp32/index.rst
b/Documentation/platforms/xtensa/esp32/index.rst
index 7a6bd10098..bec6b8dcbd 100644
--- a/Documentation/platforms/xtensa/esp32/index.rst
+++ b/Documentation/platforms/xtensa/esp32/index.rst
@@ -95,6 +95,7 @@ AES Yes
Bluetooth Yes
CAN/TWAI Yes
DMA Yes
+DAC Yes One-shot
eFuse Yes
Ethernet Yes
GPIO Yes
diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig
index b15a626940..907016808b 100644
--- a/arch/xtensa/src/esp32/Kconfig
+++ b/arch/xtensa/src/esp32/Kconfig
@@ -2355,6 +2355,35 @@ config ESP32_RTC_CLK_SRC_INT_8MD256
endchoice
endmenu # "RTC Configuration"
+menu "DAC Configuration"
+ depends on ANALOG && DAC
+
+config ESP32_DAC_DEVPATH
+ string "DAC device path"
+ default "/dev/dac0"
+
+choice ESP32_DAC_MODE
+ prompt "DAC mode of operation"
+ default ESP32_DAC_MODE_ONE_SHOT
+ ---help---
+ One-shot mode requires to write every single value with a write
call while
+ retaining the last value on output.
+
+ Following modes are not implemented yet.
+ Timer mode utilizes timer IRQs to call handler which can manage
the write.
+ DMA is using a ring buffer accessed directly by the driver.
+ Cosine Wave Generator can output preset wave without the need
to generate
+ the data and write in memory.
+
+config ESP32_DAC_MODE_ONE_SHOT
+ bool "One-shot mode"
+ ---help---
+ One-shot mode requires to write every single value with a write
call while
+ retaining the last value on output.
+
+endchoice # "DAC mode of operation"
+endmenu # "DAC Configuration"
+
menu "LEDC Configuration"
depends on ESP32_LEDC
diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs
index 2b4f908cfd..f9dad64aff 100644
--- a/arch/xtensa/src/esp32/Make.defs
+++ b/arch/xtensa/src/esp32/Make.defs
@@ -61,6 +61,10 @@ ifeq ($(CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP),y)
CHIP_CSRCS += esp32_imm.c
endif
+ifeq ($(CONFIG_DAC),y)
+CHIP_CSRCS += esp32_dac.c
+endif
+
ifeq ($(CONFIG_ESP32_LEDC),y)
CHIP_CSRCS += esp32_ledc.c
endif
diff --git a/arch/xtensa/src/esp32/esp32_dac.c
b/arch/xtensa/src/esp32/esp32_dac.c
new file mode 100644
index 0000000000..dcbe645050
--- /dev/null
+++ b/arch/xtensa/src/esp32/esp32_dac.c
@@ -0,0 +1,399 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_dac.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "xtensa.h"
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include <nuttx/analog/dac.h>
+#include <debug.h>
+#include "esp32_dac.h"
+#include "esp32_rtc_gpio.h"
+#include "hardware/esp32_rtc_io.h"
+#include "hardware/esp32_dport.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ESP32_DAC0_RTC_IO_CHANNEL RTCIO_GPIO25_CHANNEL
+#define ESP32_DAC1_RTC_IO_CHANNEL RTCIO_GPIO26_CHANNEL
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct esp32_dac_priv_s
+{
+ spinlock_t slock; /* Device specific lock. */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* DAC methods */
+
+static void dac_reset(struct dac_dev_s *dev);
+static int dac_setup(struct dac_dev_s *dev);
+static void dac_shutdown(struct dac_dev_s *dev);
+static void dac_txint(struct dac_dev_s *dev, bool enable);
+static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg);
+static int dac_ioctl(struct dac_dev_s *dev, int cmd, unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+struct esp32_dac_priv_s esp32_dac_priv;
+
+static const struct dac_ops_s g_dacops =
+{
+ .ao_reset = dac_reset,
+ .ao_setup = dac_setup,
+ .ao_shutdown = dac_shutdown,
+ .ao_txint = dac_txint,
+ .ao_send = dac_send,
+ .ao_ioctl = dac_ioctl,
+};
+
+static struct dac_dev_s g_dac =
+{
+ .ad_ops = &g_dacops, /* Arch-specific operations */
+ .ad_nchannel = 2, /* Available number of DAC channels
*/
+ .ad_priv = (void *) (&esp32_dac_priv), /* Used by the arch-specific logic */
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: dac_power
+ *
+ * Description:
+ * Power ON or OFF both DAC channels
+ *
+ * Input Parameters:
+ * bool on - true : turn DAC ON; false : turn DAC OFF
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void dac_power(bool on)
+{
+ if (on)
+ {
+ modifyreg32(RTC_IO_PAD_DAC1_REG, 0, RTC_IO_PDAC1_DAC_XPD_FORCE |
+ RTC_IO_PDAC1_XPD_DAC);
+ modifyreg32(RTC_IO_PAD_DAC2_REG, 0, RTC_IO_PDAC2_DAC_XPD_FORCE |
+ RTC_IO_PDAC2_XPD_DAC);
+ }
+ else
+ {
+ modifyreg32(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_DAC_XPD_FORCE |
+ RTC_IO_PDAC1_XPD_DAC, 0);
+ modifyreg32(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_DAC_XPD_FORCE |
+ RTC_IO_PDAC2_XPD_DAC, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: dac_reset
+ *
+ * Description:
+ * Reset the DAC channel. Called early to initialize the hardware. This
+ * is called, before dac_setup() and on error conditions.
+ *
+ * NOTE: DAC reset will reset both DAC channels!
+ *
+ * Input Parameters:
+ * dev - A pointer to the DAC device structure. This structure contains
+ * information about the DAC device.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void dac_reset(struct dac_dev_s *dev)
+{
+ dac_shutdown(dev);
+ dac_setup(dev);
+}
+
+/****************************************************************************
+ * Name: dac_setup
+ *
+ * Description:
+ * Configure the DAC. This method is called the first time that the DAC
+ * device is opened. This will occur when the port is first opened.
+ * This setup includes configuring and attaching DAC interrupts.
+ * Interrupts are all disabled upon return.
+ *
+ * Input Parameters:
+ * dev - A pointer to the DAC device structure. This structure contains
+ * information about the DAC device.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int dac_setup(struct dac_dev_s *dev)
+{
+ irqstate_t flags;
+ struct esp32_dac_priv_s *priv = (struct esp32_dac_priv_s *) dev->ad_priv;
+ ainfo("DAC starting setup (for both channels)");
+
+ flags = spin_lock_irqsave(&priv->slock);
+
+ /* Initialize RTC GPIO set to RTC Disabled and disable both pull resistors
+ * set RTC_IO_PDACn_MUX_SEL to route the pad to RTC block
+ * set RTC_IO_PDACn_DRV to 0x2 (which is default anyway)
+ * Note: Drive strength _DRV (you won't find this in TRM)
+ * 0: ~5 mA; 1: ~10 mA; 2: ~20 mA; 3: ~40 mA; the default value is 2.
+ * Keep other bits 0, especially:
+ * RTC_IO_PDACn_FUN_SEL (2 bits) = mode 0 to choose RTC_GPIO function.
+ * RTC_IO_PDACn_FUN_IE to disable Input
+ * RTC_IO_PDACn_RUE to disable pull up resistor
+ * RTC_IO_PDACn_RDE to disable pull down resistor
+ *
+ * Note: the following 2 bits are setup separately in dac_power as a last
+ * operation.
+ * set RTC_IO_PDACn_DAC_XPD_FORCE to power up DAC
+ * set RTC_IO_PDACn_XPD_DAC to power on DAC
+ */
+
+ uint32_t reg_val = RTC_IO_PDAC1_MUX_SEL |
+ 0x2 << RTC_IO_PDAC1_DRV_S;
+
+ /* Write the same value to both registers for DAC 1 and DAC 2 */
+
+ putreg32(reg_val, RTC_IO_PAD_DAC1_REG);
+ putreg32(reg_val, RTC_IO_PAD_DAC2_REG);
+
+ /* Disable GPIO output by setting bits in "write 1 to clear" reg */
+
+ modifyreg32(RTC_GPIO_ENABLE_W1TC_REG, 0 ,
+ (UINT32_C(1) << (ESP32_DAC0_RTC_IO_CHANNEL +
+ RTC_GPIO_ENABLE_W1TC_S)) |
+ (UINT32_C(1) << (ESP32_DAC1_RTC_IO_CHANNEL +
+ RTC_GPIO_ENABLE_W1TC_S)));
+
+ /* Clear bit of PAD_DRIVER to setup "normal" output mode for the
+ * corresponding pads
+ */
+
+ modifyreg32(RTC_GPIO_PIN6_REG, RTC_GPIO_PIN6_PAD_DRIVER, 0);
+ modifyreg32(RTC_GPIO_PIN7_REG, RTC_GPIO_PIN7_PAD_DRIVER, 0);
+
+ dac_power(true);
+
+ dev->ad_ocount += 1;
+
+ spin_unlock_irqrestore(&priv->slock, flags);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: dac_shutdown
+ *
+ * Description:
+ * Disable the DAC. This method is called when the DAC device is closed.
+ * This method reverses the operation the setup method.
+ *
+ * Input Parameters:
+ * dev - A pointer to the DAC device structure. This structure contains
+ * information about the DAC device.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void dac_shutdown(struct dac_dev_s *dev)
+{
+ esp32_configrtcio(ESP32_DAC0_RTC_IO_CHANNEL, RTC_FUNCTION_DIGITAL);
+ esp32_configrtcio(ESP32_DAC1_RTC_IO_CHANNEL, RTC_FUNCTION_DIGITAL);
+ dac_power(false);
+}
+
+/****************************************************************************
+ * Name: dac_txint
+ *
+ * Description:
+ * Call to enable or disable TX (transmit) interrupts for the DAC device.
+ * This function is intended to control interrupt-driven data transfers.
+ * Enabling TX interrupts allows the DAC device to generate
+ * an interrupt when it is ready to accept new data for transmission.
+ * Disabling TX interrupts would prevent the DAC from generating these
+ * interrupts.
+ *
+ * Input Parameters:
+ * dev - A pointer to the DAC device structure. This structure contains
+ * information about the DAC device.
+ * enable - Set true to enable TX interrupts. set false to disable
+ * TX interrupts.
+ *
+ * Returned Value:
+ * None
+ *
+ * Note:
+ * The actual logic for enabling or disabling TX interrupts is not
+ * implemented in this function!
+ *
+ ****************************************************************************/
+
+static void dac_txint(struct dac_dev_s *dev, bool enable)
+{
+}
+
+/****************************************************************************
+ * Name: dac_send
+ *
+ * Description:
+ * Set the DAC (Digital-to-Analog Converter) output.
+ *
+ * Input Parameters:
+ * dev - A pointer to the DAC device structure. This structure contains
+ * information about the DAC device.
+ * msg - A pointer to the DAC message structure. This structure includes
+ * the data to be sent to the DAC and the target DAC channel.
+ * The 'am_data' field of this structure is the actual data to be
+ * written to the DAC, and 'am_channel' determines which DAC channel
+ * (0 or 1) to use.
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno value on failure. -EINVAL is
+ * returned if an invalid channel is specified.
+ *
+ * Note: The dac_msg_s.am_data is treated as 8 bit value i.e. in range
+ * from 0-255 and corresponds to the analog voltage 0~Vref.
+ * The reference voltage 'Vref' here is input from the pin VDD3P3_RTC
+ * which ideally equals to the power supply VDD (3.3V).
+ * The output voltage can be calculated as the following:
+ * out_voltage = 3.3 * digi_val / 255
+ *
+ ****************************************************************************/
+
+static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg)
+{
+ irqstate_t flags;
+ uint8_t value = (uint8_t)(msg->am_data & 0xff);
+ uint32_t reg_val;
+ struct esp32_dac_priv_s *priv = (struct esp32_dac_priv_s *) dev->ad_priv;
+
+ flags = spin_lock_irqsave(&priv->slock);
+
+ switch (msg->am_channel)
+ {
+ case 0:
+ modifyreg32(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN1, 0);
+ reg_val = getreg32(RTC_IO_PAD_DAC1_REG);
+ reg_val &= ~RTC_IO_PDAC1_DAC_M;
+ reg_val |= value << RTC_IO_PDAC1_DAC_S;
+ putreg32(reg_val, RTC_IO_PAD_DAC1_REG);
+ break;
+
+ case 1:
+ modifyreg32(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN2, 0);
+ reg_val = getreg32(RTC_IO_PAD_DAC2_REG);
+ reg_val &= ~RTC_IO_PDAC2_DAC_M;
+ reg_val |= value << RTC_IO_PDAC2_DAC_S;
+ putreg32(reg_val, RTC_IO_PAD_DAC2_REG);
+ break;
+
+ default:
+ spin_unlock_irqrestore(&priv->slock, flags);
+ return -EINVAL;
+ }
+
+ spin_unlock_irqrestore(&priv->slock, flags);
+
+ /* One shot mode does not support interrupts for DAC. The TX Done is
+ * signaled to upper half driver directly from this function because the
+ * value is used right away.
+ */
+
+ dac_txdone(dev);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: dac_ioctl
+ *
+ * Description:
+ * All ioctl (input/output control) calls for the DAC device are routed
+ * through this method. This function handles various control commands
+ * for the DAC device. Currently, it returns -ENOTTY for all commands,
+ * indicating that no command is implemented.
+ *
+ * Input Parameters:
+ * dev - A pointer to the DAC device structure. This structure contains
+ * information about the DAC device, required for handling the ioctl
+ * commands.
+ * cmd - An integer value representing the ioctl command. These commands
+ * are used to perform various control operations on the DAC device.
+ * arg - An unsigned long value representing additional information or
+ * arguments that are relevant to the ioctl command.
+ * The interpretation of this parameter
+ * depends on the specific command.
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno value on failure. Currently, it
+ * always returns -ENOTTY, indicating that no ioctl commands are supported.
+ *
+ ****************************************************************************/
+
+static int dac_ioctl(struct dac_dev_s *dev, int cmd, unsigned long arg)
+{
+ return -ENOTTY;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32_dac_initialize
+ *
+ * Description:
+ * Initialize the DAC.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Valid dac device structure reference on success; a NULL on failure.
+ *
+ ****************************************************************************/
+
+struct dac_dev_s *esp32_dac_initialize(void)
+{
+ return &g_dac;
+}
diff --git a/arch/xtensa/src/esp32/esp32_dac.h
b/arch/xtensa/src/esp32/esp32_dac.h
new file mode 100644
index 0000000000..6c90d4c3da
--- /dev/null
+++ b/arch/xtensa/src/esp32/esp32_dac.h
@@ -0,0 +1,65 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_dac.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_DAC_H
+#define __ARCH_XTENSA_SRC_ESP32_ESP32_DAC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/analog/dac.h>
+#include "hardware/esp32_sens.h"
+#include "hardware/esp32_rtc_io.h"
+
+/****************************************************************************
+ * Pre-processor definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32_dac_initialize
+ *
+ * Description:
+ * Initialize the DAC.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Valid dac device structure reference on success; a NULL on failure.
+ *
+ ****************************************************************************/
+
+struct dac_dev_s *esp32_dac_initialize(void);
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_DAC_H */
diff --git a/arch/xtensa/src/esp32/hardware/esp32_sens.h
b/arch/xtensa/src/esp32/hardware/esp32_sens.h
index a172147c6c..a89bd60654 100644
--- a/arch/xtensa/src/esp32/hardware/esp32_sens.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_sens.h
@@ -35,727 +35,1464 @@
#define SENS_SAR_READ_CTRL_REG (DR_REG_SENS_BASE + 0x0)
-/* SENS_SAR1_DATA_INV : R/W; bitpos: [28]; default: 0; */
+/* SENS_SAR1_DATA_INV : RW; bitpos: [28]; default: 0;
+ * Invert SAR ADC1 data
+ */
#define SENS_SAR1_DATA_INV (BIT(28))
#define SENS_SAR1_DATA_INV_M (SENS_SAR1_DATA_INV_V << SENS_SAR1_DATA_INV_S)
-#define SENS_SAR1_DATA_INV_V 0x1
+#define SENS_SAR1_DATA_INV_V 0x00000001
#define SENS_SAR1_DATA_INV_S 28
-/* SENS_SAR1_DIG_FORCE : R/W; bitpos: [27]; default: 0; */
+/* SENS_SAR1_DIG_FORCE : RW; bitpos: [27]; default: 0;
+ * 1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC
+ * ADC1 CTRL
+ */
#define SENS_SAR1_DIG_FORCE (BIT(27))
-#define SENS_SAR1_DIG_FORCE_M (SENS_SAR1_DIG_FORCE_V << \
- SENS_SAR1_DIG_FORCE_S)
-#define SENS_SAR1_DIG_FORCE_V 0x1
+#define SENS_SAR1_DIG_FORCE_M (SENS_SAR1_DIG_FORCE_V << SENS_SAR1_DIG_FORCE_S)
+#define SENS_SAR1_DIG_FORCE_V 0x00000001
#define SENS_SAR1_DIG_FORCE_S 27
-/* SENS_SAR1_SAMPLE_BIT : R/W; bitpos: [17:16]; default: 3; */
+/* SENS_SAR1_SAMPLE_NUM : RW; bitpos: [26:19]; default: 0; */
+
+#define SENS_SAR1_SAMPLE_NUM 0x000000ff
+#define SENS_SAR1_SAMPLE_NUM_M (SENS_SAR1_SAMPLE_NUM_V <<
SENS_SAR1_SAMPLE_NUM_S)
+#define SENS_SAR1_SAMPLE_NUM_V 0x000000ff
+#define SENS_SAR1_SAMPLE_NUM_S 19
+
+/* SENS_SAR1_CLK_GATED : RW; bitpos: [18]; default: 1; */
+
+#define SENS_SAR1_CLK_GATED (BIT(18))
+#define SENS_SAR1_CLK_GATED_M (SENS_SAR1_CLK_GATED_V << SENS_SAR1_CLK_GATED_S)
+#define SENS_SAR1_CLK_GATED_V 0x00000001
+#define SENS_SAR1_CLK_GATED_S 18
+
+/* SENS_SAR1_SAMPLE_BIT : RW; bitpos: [17:16]; default: 3;
+ * 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for
+ * 12-bit width
+ */
#define SENS_SAR1_SAMPLE_BIT 0x00000003
-#define SENS_SAR1_SAMPLE_BIT_M (SENS_SAR1_SAMPLE_BIT_V << \
- SENS_SAR1_SAMPLE_BIT_S)
-#define SENS_SAR1_SAMPLE_BIT_V 0x3
+#define SENS_SAR1_SAMPLE_BIT_M (SENS_SAR1_SAMPLE_BIT_V <<
SENS_SAR1_SAMPLE_BIT_S)
+#define SENS_SAR1_SAMPLE_BIT_V 0x00000003
#define SENS_SAR1_SAMPLE_BIT_S 16
-/* SENS_SAR1_SAMPLE_CYCLE : R/W; bitpos: [15:8]; default: 9; */
+/* SENS_SAR1_SAMPLE_CYCLE : RW; bitpos: [15:8]; default: 9;
+ * sample cycles for SAR ADC1
+ */
#define SENS_SAR1_SAMPLE_CYCLE 0x000000ff
-#define SENS_SAR1_SAMPLE_CYCLE_M (SENS_SAR1_SAMPLE_CYCLE_V << \
- SENS_SAR1_SAMPLE_CYCLE_S)
-#define SENS_SAR1_SAMPLE_CYCLE_V 0xff
+#define SENS_SAR1_SAMPLE_CYCLE_M (SENS_SAR1_SAMPLE_CYCLE_V <<
SENS_SAR1_SAMPLE_CYCLE_S)
+#define SENS_SAR1_SAMPLE_CYCLE_V 0x000000ff
#define SENS_SAR1_SAMPLE_CYCLE_S 8
-/* SENS_SAR1_CLK_DIV : R/W; bitpos: [7:0]; default: 2; */
+/* SENS_SAR1_CLK_DIV : RW; bitpos: [7:0]; default: 2;
+ * clock divider
+ */
#define SENS_SAR1_CLK_DIV 0x000000ff
#define SENS_SAR1_CLK_DIV_M (SENS_SAR1_CLK_DIV_V << SENS_SAR1_CLK_DIV_S)
-#define SENS_SAR1_CLK_DIV_V 0xff
+#define SENS_SAR1_CLK_DIV_V 0x000000ff
#define SENS_SAR1_CLK_DIV_S 0
+/* SENS_SAR_READ_STATUS1_REG register */
+
+#define SENS_SAR_READ_STATUS1_REG (DR_REG_SENS_BASE + 0x4)
+
+/* SENS_SAR1_READER_STATUS : R; bitpos: [31:0]; default: 0; */
+
+#define SENS_SAR1_READER_STATUS 0xffffffff
+#define SENS_SAR1_READER_STATUS_M (SENS_SAR1_READER_STATUS_V <<
SENS_SAR1_READER_STATUS_S)
+#define SENS_SAR1_READER_STATUS_V 0xffffffff
+#define SENS_SAR1_READER_STATUS_S 0
+
+/* SENS_SAR_MEAS_WAIT1_REG register */
+
+#define SENS_SAR_MEAS_WAIT1_REG (DR_REG_SENS_BASE + 0x8)
+
+/* SENS_SAR_AMP_WAIT2 : RW; bitpos: [31:16]; default: 10; */
+
+#define SENS_SAR_AMP_WAIT2 0x0000ffff
+#define SENS_SAR_AMP_WAIT2_M (SENS_SAR_AMP_WAIT2_V << SENS_SAR_AMP_WAIT2_S)
+#define SENS_SAR_AMP_WAIT2_V 0x0000ffff
+#define SENS_SAR_AMP_WAIT2_S 16
+
+/* SENS_SAR_AMP_WAIT1 : RW; bitpos: [15:0]; default: 10; */
+
+#define SENS_SAR_AMP_WAIT1 0x0000ffff
+#define SENS_SAR_AMP_WAIT1_M (SENS_SAR_AMP_WAIT1_V << SENS_SAR_AMP_WAIT1_S)
+#define SENS_SAR_AMP_WAIT1_V 0x0000ffff
+#define SENS_SAR_AMP_WAIT1_S 0
+
+/* SENS_SAR_MEAS_WAIT2_REG register */
+
+#define SENS_SAR_MEAS_WAIT2_REG (DR_REG_SENS_BASE + 0xc)
+
+/* SENS_SAR2_RSTB_WAIT : RW; bitpos: [27:20]; default: 2; */
+
+#define SENS_SAR2_RSTB_WAIT 0x000000ff
+#define SENS_SAR2_RSTB_WAIT_M (SENS_SAR2_RSTB_WAIT_V << SENS_SAR2_RSTB_WAIT_S)
+#define SENS_SAR2_RSTB_WAIT_V 0x000000ff
+#define SENS_SAR2_RSTB_WAIT_S 20
+
+/* SENS_FORCE_XPD_SAR : RW; bitpos: [19:18]; default: 0; */
+
+#define SENS_FORCE_XPD_SAR 0x00000003
+#define SENS_FORCE_XPD_SAR_M (SENS_FORCE_XPD_SAR_V << SENS_FORCE_XPD_SAR_S)
+#define SENS_FORCE_XPD_SAR_V 0x00000003
+#define SENS_FORCE_XPD_SAR_S 18
+
+/* SENS_FORCE_XPD_AMP : RW; bitpos: [17:16]; default: 0; */
+
+#define SENS_FORCE_XPD_AMP 0x00000003
+#define SENS_FORCE_XPD_AMP_M (SENS_FORCE_XPD_AMP_V << SENS_FORCE_XPD_AMP_S)
+#define SENS_FORCE_XPD_AMP_V 0x00000003
+#define SENS_FORCE_XPD_AMP_S 16
+
+/* SENS_SAR_AMP_WAIT3 : RW; bitpos: [15:0]; default: 10; */
+
+#define SENS_SAR_AMP_WAIT3 0x0000ffff
+#define SENS_SAR_AMP_WAIT3_M (SENS_SAR_AMP_WAIT3_V << SENS_SAR_AMP_WAIT3_S)
+#define SENS_SAR_AMP_WAIT3_V 0x0000ffff
+#define SENS_SAR_AMP_WAIT3_S 0
+
+/* SENS_FORCE_XPD_SAR_SW : RW; bitpos: [-1:0]; default: 0; */
+
+#define SENS_FORCE_XPD_SAR_SW 0x00000000
+#define SENS_FORCE_XPD_SAR_SW_M (SENS_FORCE_XPD_SAR_SW_V <<
SENS_FORCE_XPD_SAR_SW_S)
+#define SENS_FORCE_XPD_SAR_SW_V 0x00000000
+#define SENS_FORCE_XPD_SAR_SW_S 0
+
+/* SENS_SAR_MEAS_CTRL_REG register */
+
+#define SENS_SAR_MEAS_CTRL_REG (DR_REG_SENS_BASE + 0x10)
+
+/* SENS_SAR2_XPD_WAIT : RW; bitpos: [31:24]; default: 7; */
+
+#define SENS_SAR2_XPD_WAIT 0x000000ff
+#define SENS_SAR2_XPD_WAIT_M (SENS_SAR2_XPD_WAIT_V << SENS_SAR2_XPD_WAIT_S)
+#define SENS_SAR2_XPD_WAIT_V 0x000000ff
+#define SENS_SAR2_XPD_WAIT_S 24
+
+/* SENS_SAR_RSTB_FSM : RW; bitpos: [23:20]; default: 0; */
+
+#define SENS_SAR_RSTB_FSM 0x0000000f
+#define SENS_SAR_RSTB_FSM_M (SENS_SAR_RSTB_FSM_V << SENS_SAR_RSTB_FSM_S)
+#define SENS_SAR_RSTB_FSM_V 0x0000000f
+#define SENS_SAR_RSTB_FSM_S 20
+
+/* SENS_XPD_SAR_FSM : RW; bitpos: [19:16]; default: 7; */
+
+#define SENS_XPD_SAR_FSM 0x0000000f
+#define SENS_XPD_SAR_FSM_M (SENS_XPD_SAR_FSM_V << SENS_XPD_SAR_FSM_S)
+#define SENS_XPD_SAR_FSM_V 0x0000000f
+#define SENS_XPD_SAR_FSM_S 16
+
+/* SENS_AMP_SHORT_REF_GND_FSM : RW; bitpos: [15:12]; default: 3; */
+
+#define SENS_AMP_SHORT_REF_GND_FSM 0x0000000f
+#define SENS_AMP_SHORT_REF_GND_FSM_M (SENS_AMP_SHORT_REF_GND_FSM_V <<
SENS_AMP_SHORT_REF_GND_FSM_S)
+#define SENS_AMP_SHORT_REF_GND_FSM_V 0x0000000f
+#define SENS_AMP_SHORT_REF_GND_FSM_S 12
+
+/* SENS_AMP_SHORT_REF_FSM : RW; bitpos: [11:8]; default: 3; */
+
+#define SENS_AMP_SHORT_REF_FSM 0x0000000f
+#define SENS_AMP_SHORT_REF_FSM_M (SENS_AMP_SHORT_REF_FSM_V <<
SENS_AMP_SHORT_REF_FSM_S)
+#define SENS_AMP_SHORT_REF_FSM_V 0x0000000f
+#define SENS_AMP_SHORT_REF_FSM_S 8
+
+/* SENS_AMP_RST_FB_FSM : RW; bitpos: [7:4]; default: 8; */
+
+#define SENS_AMP_RST_FB_FSM 0x0000000f
+#define SENS_AMP_RST_FB_FSM_M (SENS_AMP_RST_FB_FSM_V << SENS_AMP_RST_FB_FSM_S)
+#define SENS_AMP_RST_FB_FSM_V 0x0000000f
+#define SENS_AMP_RST_FB_FSM_S 4
+
+/* SENS_XPD_SAR_AMP_FSM : RW; bitpos: [3:0]; default: 15; */
+
+#define SENS_XPD_SAR_AMP_FSM 0x0000000f
+#define SENS_XPD_SAR_AMP_FSM_M (SENS_XPD_SAR_AMP_FSM_V <<
SENS_XPD_SAR_AMP_FSM_S)
+#define SENS_XPD_SAR_AMP_FSM_V 0x0000000f
+#define SENS_XPD_SAR_AMP_FSM_S 0
+
+/* SENS_SAR_READ_STATUS2_REG register */
+
+#define SENS_SAR_READ_STATUS2_REG (DR_REG_SENS_BASE + 0x14)
+
+/* SENS_SAR2_READER_STATUS : R; bitpos: [31:0]; default: 0; */
+
+#define SENS_SAR2_READER_STATUS 0xffffffff
+#define SENS_SAR2_READER_STATUS_M (SENS_SAR2_READER_STATUS_V <<
SENS_SAR2_READER_STATUS_S)
+#define SENS_SAR2_READER_STATUS_V 0xffffffff
+#define SENS_SAR2_READER_STATUS_S 0
+
/* SENS_ULP_CP_SLEEP_CYC0_REG register */
#define SENS_ULP_CP_SLEEP_CYC0_REG (DR_REG_SENS_BASE + 0x18)
-/* SENS_ULP_CP_SLEEP_CYC0 : R/W; bitpos: [31:0]; default: 200; */
+/* SENS_SLEEP_CYCLES_S0 : RW; bitpos: [31:0]; default: 200;
+ * sleep cycles for ULP-coprocessor timer
+ */
+
+#define SENS_SLEEP_CYCLES_S0 0xffffffff
+#define SENS_SLEEP_CYCLES_S0_M (SENS_SLEEP_CYCLES_S0_V <<
SENS_SLEEP_CYCLES_S0_S)
+#define SENS_SLEEP_CYCLES_S0_V 0xffffffff
+#define SENS_SLEEP_CYCLES_S0_S 0
+
+/* SENS_ULP_CP_SLEEP_CYC1_REG register */
+
+#define SENS_ULP_CP_SLEEP_CYC1_REG (DR_REG_SENS_BASE + 0x1c)
+
+/* SENS_SLEEP_CYCLES_S1 : RW; bitpos: [31:0]; default: 100; */
+
+#define SENS_SLEEP_CYCLES_S1 0xffffffff
+#define SENS_SLEEP_CYCLES_S1_M (SENS_SLEEP_CYCLES_S1_V <<
SENS_SLEEP_CYCLES_S1_S)
+#define SENS_SLEEP_CYCLES_S1_V 0xffffffff
+#define SENS_SLEEP_CYCLES_S1_S 0
+
+/* SENS_ULP_CP_SLEEP_CYC2_REG register */
+
+#define SENS_ULP_CP_SLEEP_CYC2_REG (DR_REG_SENS_BASE + 0x20)
+
+/* SENS_SLEEP_CYCLES_S2 : RW; bitpos: [31:0]; default: 50; */
+
+#define SENS_SLEEP_CYCLES_S2 0xffffffff
+#define SENS_SLEEP_CYCLES_S2_M (SENS_SLEEP_CYCLES_S2_V <<
SENS_SLEEP_CYCLES_S2_S)
+#define SENS_SLEEP_CYCLES_S2_V 0xffffffff
+#define SENS_SLEEP_CYCLES_S2_S 0
+
+/* SENS_ULP_CP_SLEEP_CYC3_REG register */
-#define SENS_ULP_CP_SLEEP_CYC0 0xffffffff
-#define SENS_ULP_CP_SLEEP_CYC0_M (SENS_ULP_CP_SLEEP_CYC0_V << \
- SENS_ULP_CP_SLEEP_CYC0_S)
-#define SENS_ULP_CP_SLEEP_CYC0_V 0xffffffff
-#define SENS_ULP_CP_SLEEP_CYC0_S 0
+#define SENS_ULP_CP_SLEEP_CYC3_REG (DR_REG_SENS_BASE + 0x24)
+
+/* SENS_SLEEP_CYCLES_S3 : RW; bitpos: [31:0]; default: 40; */
+
+#define SENS_SLEEP_CYCLES_S3 0xffffffff
+#define SENS_SLEEP_CYCLES_S3_M (SENS_SLEEP_CYCLES_S3_V <<
SENS_SLEEP_CYCLES_S3_S)
+#define SENS_SLEEP_CYCLES_S3_V 0xffffffff
+#define SENS_SLEEP_CYCLES_S3_S 0
+
+/* SENS_ULP_CP_SLEEP_CYC4_REG register */
+
+#define SENS_ULP_CP_SLEEP_CYC4_REG (DR_REG_SENS_BASE + 0x28)
+
+/* SENS_SLEEP_CYCLES_S4 : RW; bitpos: [31:0]; default: 20; */
+
+#define SENS_SLEEP_CYCLES_S4 0xffffffff
+#define SENS_SLEEP_CYCLES_S4_M (SENS_SLEEP_CYCLES_S4_V <<
SENS_SLEEP_CYCLES_S4_S)
+#define SENS_SLEEP_CYCLES_S4_V 0xffffffff
+#define SENS_SLEEP_CYCLES_S4_S 0
/* SENS_SAR_START_FORCE_REG register */
#define SENS_SAR_START_FORCE_REG (DR_REG_SENS_BASE + 0x2c)
-/* SENS_SAR1_STOP : R/W; bitpos: [23]; default: 0; */
+/* SENS_SAR2_PWDET_EN : RW; bitpos: [24]; default: 0;
+ * N/A
+ */
+
+#define SENS_SAR2_PWDET_EN (BIT(24))
+#define SENS_SAR2_PWDET_EN_M (SENS_SAR2_PWDET_EN_V << SENS_SAR2_PWDET_EN_S)
+#define SENS_SAR2_PWDET_EN_V 0x00000001
+#define SENS_SAR2_PWDET_EN_S 24
+
+/* SENS_SAR1_STOP : RW; bitpos: [23]; default: 0;
+ * stop SAR ADC1 conversion
+ */
#define SENS_SAR1_STOP (BIT(23))
#define SENS_SAR1_STOP_M (SENS_SAR1_STOP_V << SENS_SAR1_STOP_S)
-#define SENS_SAR1_STOP_V 0x1
+#define SENS_SAR1_STOP_V 0x00000001
#define SENS_SAR1_STOP_S 23
-/* SENS_SAR2_STOP : R/W; bitpos: [22]; default: 0; */
+/* SENS_SAR2_STOP : RW; bitpos: [22]; default: 0;
+ * stop SAR ADC2 conversion
+ */
#define SENS_SAR2_STOP (BIT(22))
#define SENS_SAR2_STOP_M (SENS_SAR2_STOP_V << SENS_SAR2_STOP_S)
-#define SENS_SAR2_STOP_V 0x1
+#define SENS_SAR2_STOP_V 0x00000001
#define SENS_SAR2_STOP_S 22
-/* SENS_PC_INIT : R/W; bitpos: [21:11]; default: 0; */
+/* SENS_PC_INIT : RW; bitpos: [21:11]; default: 0;
+ * initialized PC for ULP-coprocessor
+ */
#define SENS_PC_INIT 0x000007ff
#define SENS_PC_INIT_M (SENS_PC_INIT_V << SENS_PC_INIT_S)
-#define SENS_PC_INIT_V 0x7ff
+#define SENS_PC_INIT_V 0x000007ff
#define SENS_PC_INIT_S 11
-/* SENS_ULP_CP_START_TOP : R/W; bitpos: [9]; default: 0; */
+/* SENS_SARCLK_EN : RW; bitpos: [10]; default: 0; */
+
+#define SENS_SARCLK_EN (BIT(10))
+#define SENS_SARCLK_EN_M (SENS_SARCLK_EN_V << SENS_SARCLK_EN_S)
+#define SENS_SARCLK_EN_V 0x00000001
+#define SENS_SARCLK_EN_S 10
+
+/* SENS_ULP_CP_START_TOP : RW; bitpos: [9]; default: 0;
+ * Write 1 to start ULP-coprocessor only active when
+ * reg_ulp_cp_force_start_top = 1
+ */
#define SENS_ULP_CP_START_TOP (BIT(9))
-#define SENS_ULP_CP_START_TOP_M (SENS_ULP_CP_START_TOP_V << \
- SENS_ULP_CP_START_TOP_S)
-#define SENS_ULP_CP_START_TOP_V 0x1
+#define SENS_ULP_CP_START_TOP_M (SENS_ULP_CP_START_TOP_V <<
SENS_ULP_CP_START_TOP_S)
+#define SENS_ULP_CP_START_TOP_V 0x00000001
#define SENS_ULP_CP_START_TOP_S 9
-/* SENS_ULP_CP_FORCE_START_TOP : R/W; bitpos: [8]; default: 0; */
+/* SENS_ULP_CP_FORCE_START_TOP : RW; bitpos: [8]; default: 0;
+ * 1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by
+ * timer
+ */
#define SENS_ULP_CP_FORCE_START_TOP (BIT(8))
-#define SENS_ULP_CP_FORCE_START_TOP_M (SENS_ULP_CP_FORCE_START_TOP_V << \
- SENS_ULP_CP_FORCE_START_TOP_S)
-#define SENS_ULP_CP_FORCE_START_TOP_V 0x1
+#define SENS_ULP_CP_FORCE_START_TOP_M (SENS_ULP_CP_FORCE_START_TOP_V <<
SENS_ULP_CP_FORCE_START_TOP_S)
+#define SENS_ULP_CP_FORCE_START_TOP_V 0x00000001
#define SENS_ULP_CP_FORCE_START_TOP_S 8
-/* SENS_SAR2_PWDET_CCT : R/W; bitpos: [7:5]; default: 0; */
+/* SENS_SAR2_PWDET_CCT : RW; bitpos: [7:5]; default: 0;
+ * SAR2_PWDET_CCT PA power detector capacitance tuning.
+ */
#define SENS_SAR2_PWDET_CCT 0x00000007
-#define SENS_SAR2_PWDET_CCT_M (SENS_SAR2_PWDET_CCT_V << \
- SENS_SAR2_PWDET_CCT_S)
-#define SENS_SAR2_PWDET_CCT_V 0x7
+#define SENS_SAR2_PWDET_CCT_M (SENS_SAR2_PWDET_CCT_V << SENS_SAR2_PWDET_CCT_S)
+#define SENS_SAR2_PWDET_CCT_V 0x00000007
#define SENS_SAR2_PWDET_CCT_S 5
-/* SENS_SAR2_EN_TEST : R/W; bitpos: [4]; default: 0; */
+/* SENS_SAR2_EN_TEST : RW; bitpos: [4]; default: 0;
+ * SAR2_EN_TEST only active when reg_sar2_dig_force = 0
+ */
#define SENS_SAR2_EN_TEST (BIT(4))
#define SENS_SAR2_EN_TEST_M (SENS_SAR2_EN_TEST_V << SENS_SAR2_EN_TEST_S)
-#define SENS_SAR2_EN_TEST_V 0x1
+#define SENS_SAR2_EN_TEST_V 0x00000001
#define SENS_SAR2_EN_TEST_S 4
-/* SENS_SAR2_BIT_WIDTH : R/W; bitpos: [3:2]; default: 3; */
+/* SENS_SAR2_BIT_WIDTH : RW; bitpos: [3:2]; default: 3;
+ * 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits
+ */
#define SENS_SAR2_BIT_WIDTH 0x00000003
-#define SENS_SAR2_BIT_WIDTH_M (SENS_SAR2_BIT_WIDTH_V << \
- SENS_SAR2_BIT_WIDTH_S)
-#define SENS_SAR2_BIT_WIDTH_V 0x3
+#define SENS_SAR2_BIT_WIDTH_M (SENS_SAR2_BIT_WIDTH_V << SENS_SAR2_BIT_WIDTH_S)
+#define SENS_SAR2_BIT_WIDTH_V 0x00000003
#define SENS_SAR2_BIT_WIDTH_S 2
-/* SENS_SAR1_BIT_WIDTH : R/W; bitpos: [1:0]; default: 3; */
+/* SENS_SAR1_BIT_WIDTH : RW; bitpos: [1:0]; default: 3;
+ * 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits
+ */
#define SENS_SAR1_BIT_WIDTH 0x00000003
-#define SENS_SAR1_BIT_WIDTH_M (SENS_SAR1_BIT_WIDTH_V << \
- SENS_SAR1_BIT_WIDTH_S)
-#define SENS_SAR1_BIT_WIDTH_V 0x3
+#define SENS_SAR1_BIT_WIDTH_M (SENS_SAR1_BIT_WIDTH_V << SENS_SAR1_BIT_WIDTH_S)
+#define SENS_SAR1_BIT_WIDTH_V 0x00000003
#define SENS_SAR1_BIT_WIDTH_S 0
+/* SENS_SAR_MEM_WR_CTRL_REG register */
+
+#define SENS_SAR_MEM_WR_CTRL_REG (DR_REG_SENS_BASE + 0x30)
+
+/* SENS_RTC_MEM_WR_OFFST_CLR : W; bitpos: [22]; default: 0; */
+
+#define SENS_RTC_MEM_WR_OFFST_CLR (BIT(22))
+#define SENS_RTC_MEM_WR_OFFST_CLR_M (SENS_RTC_MEM_WR_OFFST_CLR_V <<
SENS_RTC_MEM_WR_OFFST_CLR_S)
+#define SENS_RTC_MEM_WR_OFFST_CLR_V 0x00000001
+#define SENS_RTC_MEM_WR_OFFST_CLR_S 22
+
+/* SENS_MEM_WR_ADDR_SIZE : RW; bitpos: [21:11]; default: 512; */
+
+#define SENS_MEM_WR_ADDR_SIZE 0x000007ff
+#define SENS_MEM_WR_ADDR_SIZE_M (SENS_MEM_WR_ADDR_SIZE_V <<
SENS_MEM_WR_ADDR_SIZE_S)
+#define SENS_MEM_WR_ADDR_SIZE_V 0x000007ff
+#define SENS_MEM_WR_ADDR_SIZE_S 11
+
+/* SENS_MEM_WR_ADDR_INIT : RW; bitpos: [10:0]; default: 512; */
+
+#define SENS_MEM_WR_ADDR_INIT 0x000007ff
+#define SENS_MEM_WR_ADDR_INIT_M (SENS_MEM_WR_ADDR_INIT_V <<
SENS_MEM_WR_ADDR_INIT_S)
+#define SENS_MEM_WR_ADDR_INIT_V 0x000007ff
+#define SENS_MEM_WR_ADDR_INIT_S 0
+
/* SENS_SAR_ATTEN1_REG register */
#define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x34)
-/* SENS_SAR_ATTEN1 : R/W; bitpos: [31:0]; default: 0xffffffff; */
+/* SENS_SAR1_ATTEN : RW; bitpos: [31:0]; default: 4294967295;
+ * 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB
+ */
-#define SENS_SAR_ATTEN1 0xffffffff
-#define SENS_SAR_ATTEN1_M (SENS_SAR_ATTEN1_V << SENS_SAR_ATTEN1_S)
-#define SENS_SAR_ATTEN1_V 0xffffffff
-#define SENS_SAR_ATTEN1_S 0
+#define SENS_SAR1_ATTEN 0xffffffff
+#define SENS_SAR1_ATTEN_M (SENS_SAR1_ATTEN_V << SENS_SAR1_ATTEN_S)
+#define SENS_SAR1_ATTEN_V 0xffffffff
+#define SENS_SAR1_ATTEN_S 0
/* SENS_SAR_ATTEN2_REG register */
#define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x38)
-/* SENS_SAR_ATTEN2 : R/W; bitpos: [31:0]; default: 0xffffffff; */
+/* SENS_SAR2_ATTEN : RW; bitpos: [31:0]; default: 4294967295;
+ * 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB
+ */
+
+#define SENS_SAR2_ATTEN 0xffffffff
+#define SENS_SAR2_ATTEN_M (SENS_SAR2_ATTEN_V << SENS_SAR2_ATTEN_S)
+#define SENS_SAR2_ATTEN_V 0xffffffff
+#define SENS_SAR2_ATTEN_S 0
+
+/* SENS_SAR_SLAVE_ADDR1_REG register */
+
+#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x3c)
+
+/* SENS_MEAS_STATUS : R; bitpos: [29:22]; default: 0; */
+
+#define SENS_MEAS_STATUS 0x000000ff
+#define SENS_MEAS_STATUS_M (SENS_MEAS_STATUS_V << SENS_MEAS_STATUS_S)
+#define SENS_MEAS_STATUS_V 0x000000ff
+#define SENS_MEAS_STATUS_S 22
+
+/* SENS_I2C_SLAVE_ADDR0 : RW; bitpos: [21:11]; default: 0; */
+
+#define SENS_I2C_SLAVE_ADDR0 0x000007ff
+#define SENS_I2C_SLAVE_ADDR0_M (SENS_I2C_SLAVE_ADDR0_V <<
SENS_I2C_SLAVE_ADDR0_S)
+#define SENS_I2C_SLAVE_ADDR0_V 0x000007ff
+#define SENS_I2C_SLAVE_ADDR0_S 11
+
+/* SENS_I2C_SLAVE_ADDR1 : RW; bitpos: [10:0]; default: 0; */
+
+#define SENS_I2C_SLAVE_ADDR1 0x000007ff
+#define SENS_I2C_SLAVE_ADDR1_M (SENS_I2C_SLAVE_ADDR1_V <<
SENS_I2C_SLAVE_ADDR1_S)
+#define SENS_I2C_SLAVE_ADDR1_V 0x000007ff
+#define SENS_I2C_SLAVE_ADDR1_S 0
+
+/* SENS_SAR_SLAVE_ADDR2_REG register */
+
+#define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x40)
+
+/* SENS_I2C_SLAVE_ADDR2 : RW; bitpos: [21:11]; default: 0; */
+
+#define SENS_I2C_SLAVE_ADDR2 0x000007ff
+#define SENS_I2C_SLAVE_ADDR2_M (SENS_I2C_SLAVE_ADDR2_V <<
SENS_I2C_SLAVE_ADDR2_S)
+#define SENS_I2C_SLAVE_ADDR2_V 0x000007ff
+#define SENS_I2C_SLAVE_ADDR2_S 11
+
+/* SENS_I2C_SLAVE_ADDR3 : RW; bitpos: [10:0]; default: 0; */
+
+#define SENS_I2C_SLAVE_ADDR3 0x000007ff
+#define SENS_I2C_SLAVE_ADDR3_M (SENS_I2C_SLAVE_ADDR3_V <<
SENS_I2C_SLAVE_ADDR3_S)
+#define SENS_I2C_SLAVE_ADDR3_V 0x000007ff
+#define SENS_I2C_SLAVE_ADDR3_S 0
-#define SENS_SAR_ATTEN2 0xffffffff
-#define SENS_SAR_ATTEN2_M (SENS_SAR_ATTEN2_V << SENS_SAR_ATTEN2_S)
-#define SENS_SAR_ATTEN2_V 0xffffffff
-#define SENS_SAR_ATTEN2_S 0
+/* SENS_SAR_SLAVE_ADDR3_REG register */
+
+#define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x44)
+
+/* SENS_TSENS_RDY_OUT : R; bitpos: [30]; default: 0;
+ * indicate temperature sensor out ready
+ */
+
+#define SENS_TSENS_RDY_OUT (BIT(30))
+#define SENS_TSENS_RDY_OUT_M (SENS_TSENS_RDY_OUT_V << SENS_TSENS_RDY_OUT_S)
+#define SENS_TSENS_RDY_OUT_V 0x00000001
+#define SENS_TSENS_RDY_OUT_S 30
+
+/* SENS_TSENS_OUT : R; bitpos: [29:22]; default: 0;
+ * temperature sensor data out
+ */
+
+#define SENS_TSENS_OUT 0x000000ff
+#define SENS_TSENS_OUT_M (SENS_TSENS_OUT_V << SENS_TSENS_OUT_S)
+#define SENS_TSENS_OUT_V 0x000000ff
+#define SENS_TSENS_OUT_S 22
+
+/* SENS_I2C_SLAVE_ADDR4 : RW; bitpos: [21:11]; default: 0; */
+
+#define SENS_I2C_SLAVE_ADDR4 0x000007ff
+#define SENS_I2C_SLAVE_ADDR4_M (SENS_I2C_SLAVE_ADDR4_V <<
SENS_I2C_SLAVE_ADDR4_S)
+#define SENS_I2C_SLAVE_ADDR4_V 0x000007ff
+#define SENS_I2C_SLAVE_ADDR4_S 11
+
+/* SENS_I2C_SLAVE_ADDR5 : RW; bitpos: [10:0]; default: 0; */
+
+#define SENS_I2C_SLAVE_ADDR5 0x000007ff
+#define SENS_I2C_SLAVE_ADDR5_M (SENS_I2C_SLAVE_ADDR5_V <<
SENS_I2C_SLAVE_ADDR5_S)
+#define SENS_I2C_SLAVE_ADDR5_V 0x000007ff
+#define SENS_I2C_SLAVE_ADDR5_S 0
+
+/* SENS_SAR_SLAVE_ADDR4_REG register */
+
+#define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x48)
+
+/* SENS_I2C_DONE : R; bitpos: [30]; default: 0;
+ * indicate I2C done
+ */
+
+#define SENS_I2C_DONE (BIT(30))
+#define SENS_I2C_DONE_M (SENS_I2C_DONE_V << SENS_I2C_DONE_S)
+#define SENS_I2C_DONE_V 0x00000001
+#define SENS_I2C_DONE_S 30
+
+/* SENS_I2C_RDATA : R; bitpos: [29:22]; default: 0;
+ * I2C read data
+ */
+
+#define SENS_I2C_RDATA 0x000000ff
+#define SENS_I2C_RDATA_M (SENS_I2C_RDATA_V << SENS_I2C_RDATA_S)
+#define SENS_I2C_RDATA_V 0x000000ff
+#define SENS_I2C_RDATA_S 22
+
+/* SENS_I2C_SLAVE_ADDR6 : RW; bitpos: [21:11]; default: 0; */
+
+#define SENS_I2C_SLAVE_ADDR6 0x000007ff
+#define SENS_I2C_SLAVE_ADDR6_M (SENS_I2C_SLAVE_ADDR6_V <<
SENS_I2C_SLAVE_ADDR6_S)
+#define SENS_I2C_SLAVE_ADDR6_V 0x000007ff
+#define SENS_I2C_SLAVE_ADDR6_S 11
+
+/* SENS_I2C_SLAVE_ADDR7 : RW; bitpos: [10:0]; default: 0; */
+
+#define SENS_I2C_SLAVE_ADDR7 0x000007ff
+#define SENS_I2C_SLAVE_ADDR7_M (SENS_I2C_SLAVE_ADDR7_V <<
SENS_I2C_SLAVE_ADDR7_S)
+#define SENS_I2C_SLAVE_ADDR7_V 0x000007ff
+#define SENS_I2C_SLAVE_ADDR7_S 0
+
+/* SENS_SAR_TSENS_CTRL_REG register */
+
+#define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x4c)
+
+/* SENS_TSENS_DUMP_OUT : RW; bitpos: [26]; default: 0;
+ * temperature sensor dump out only active when reg_tsens_power_up_force = 1
+ */
+
+#define SENS_TSENS_DUMP_OUT (BIT(26))
+#define SENS_TSENS_DUMP_OUT_M (SENS_TSENS_DUMP_OUT_V << SENS_TSENS_DUMP_OUT_S)
+#define SENS_TSENS_DUMP_OUT_V 0x00000001
+#define SENS_TSENS_DUMP_OUT_S 26
+
+/* SENS_TSENS_POWER_UP_FORCE : RW; bitpos: [25]; default: 0;
+ * 1: dump out & power up controlled by SW 0: by FSM
+ */
+
+#define SENS_TSENS_POWER_UP_FORCE (BIT(25))
+#define SENS_TSENS_POWER_UP_FORCE_M (SENS_TSENS_POWER_UP_FORCE_V <<
SENS_TSENS_POWER_UP_FORCE_S)
+#define SENS_TSENS_POWER_UP_FORCE_V 0x00000001
+#define SENS_TSENS_POWER_UP_FORCE_S 25
+
+/* SENS_TSENS_POWER_UP : RW; bitpos: [24]; default: 0;
+ * temperature sensor power up
+ */
+
+#define SENS_TSENS_POWER_UP (BIT(24))
+#define SENS_TSENS_POWER_UP_M (SENS_TSENS_POWER_UP_V << SENS_TSENS_POWER_UP_S)
+#define SENS_TSENS_POWER_UP_V 0x00000001
+#define SENS_TSENS_POWER_UP_S 24
+
+/* SENS_TSENS_CLK_DIV : RW; bitpos: [23:16]; default: 6;
+ * temperature sensor clock divider
+ */
+
+#define SENS_TSENS_CLK_DIV 0x000000ff
+#define SENS_TSENS_CLK_DIV_M (SENS_TSENS_CLK_DIV_V << SENS_TSENS_CLK_DIV_S)
+#define SENS_TSENS_CLK_DIV_V 0x000000ff
+#define SENS_TSENS_CLK_DIV_S 16
+
+/* SENS_TSENS_IN_INV : RW; bitpos: [15]; default: 0;
+ * invert temperature sensor data
+ */
+
+#define SENS_TSENS_IN_INV (BIT(15))
+#define SENS_TSENS_IN_INV_M (SENS_TSENS_IN_INV_V << SENS_TSENS_IN_INV_S)
+#define SENS_TSENS_IN_INV_V 0x00000001
+#define SENS_TSENS_IN_INV_S 15
+
+/* SENS_TSENS_CLK_GATED : RW; bitpos: [14]; default: 1; */
+
+#define SENS_TSENS_CLK_GATED (BIT(14))
+#define SENS_TSENS_CLK_GATED_M (SENS_TSENS_CLK_GATED_V <<
SENS_TSENS_CLK_GATED_S)
+#define SENS_TSENS_CLK_GATED_V 0x00000001
+#define SENS_TSENS_CLK_GATED_S 14
+
+/* SENS_TSENS_CLK_INV : RW; bitpos: [13]; default: 1; */
+
+#define SENS_TSENS_CLK_INV (BIT(13))
+#define SENS_TSENS_CLK_INV_M (SENS_TSENS_CLK_INV_V << SENS_TSENS_CLK_INV_S)
+#define SENS_TSENS_CLK_INV_V 0x00000001
+#define SENS_TSENS_CLK_INV_S 13
+
+/* SENS_TSENS_XPD_FORCE : RW; bitpos: [12]; default: 0; */
+
+#define SENS_TSENS_XPD_FORCE (BIT(12))
+#define SENS_TSENS_XPD_FORCE_M (SENS_TSENS_XPD_FORCE_V <<
SENS_TSENS_XPD_FORCE_S)
+#define SENS_TSENS_XPD_FORCE_V 0x00000001
+#define SENS_TSENS_XPD_FORCE_S 12
+
+/* SENS_TSENS_XPD_WAIT : RW; bitpos: [11:0]; default: 2; */
+
+#define SENS_TSENS_XPD_WAIT 0x00000fff
+#define SENS_TSENS_XPD_WAIT_M (SENS_TSENS_XPD_WAIT_V << SENS_TSENS_XPD_WAIT_S)
+#define SENS_TSENS_XPD_WAIT_V 0x00000fff
+#define SENS_TSENS_XPD_WAIT_S 0
+
+/* SENS_SAR_I2C_CTRL_REG register */
+
+#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x50)
+
+/* SENS_SAR_I2C_START_FORCE : RW; bitpos: [29]; default: 0;
+ * 1: I2C started by SW 0: I2C started by FSM
+ */
+
+#define SENS_SAR_I2C_START_FORCE (BIT(29))
+#define SENS_SAR_I2C_START_FORCE_M (SENS_SAR_I2C_START_FORCE_V <<
SENS_SAR_I2C_START_FORCE_S)
+#define SENS_SAR_I2C_START_FORCE_V 0x00000001
+#define SENS_SAR_I2C_START_FORCE_S 29
+
+/* SENS_SAR_I2C_START : RW; bitpos: [28]; default: 0;
+ * start I2C only active when reg_sar_i2c_start_force = 1
+ */
+
+#define SENS_SAR_I2C_START (BIT(28))
+#define SENS_SAR_I2C_START_M (SENS_SAR_I2C_START_V << SENS_SAR_I2C_START_S)
+#define SENS_SAR_I2C_START_V 0x00000001
+#define SENS_SAR_I2C_START_S 28
+
+/* SENS_SAR_I2C_CTRL : RW; bitpos: [27:0]; default: 0;
+ * I2C control data only active when reg_sar_i2c_start_force = 1
+ */
+
+#define SENS_SAR_I2C_CTRL 0x0fffffff
+#define SENS_SAR_I2C_CTRL_M (SENS_SAR_I2C_CTRL_V << SENS_SAR_I2C_CTRL_S)
+#define SENS_SAR_I2C_CTRL_V 0x0fffffff
+#define SENS_SAR_I2C_CTRL_S 0
/* SENS_SAR_MEAS_START1_REG register */
#define SENS_SAR_MEAS_START1_REG (DR_REG_SENS_BASE + 0x54)
-/* SENS_SAR1_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0; */
+/* SENS_SAR1_EN_PAD_FORCE : RW; bitpos: [31]; default: 0;
+ * 1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 pad enable
+ * bitmap is controlled by ULP-coprocessor
+ */
#define SENS_SAR1_EN_PAD_FORCE (BIT(31))
-#define SENS_SAR1_EN_PAD_FORCE_M (SENS_SAR1_EN_PAD_FORCE_V << \
- SENS_SAR1_EN_PAD_FORCE_S)
-#define SENS_SAR1_EN_PAD_FORCE_V 0x1
+#define SENS_SAR1_EN_PAD_FORCE_M (SENS_SAR1_EN_PAD_FORCE_V <<
SENS_SAR1_EN_PAD_FORCE_S)
+#define SENS_SAR1_EN_PAD_FORCE_V 0x00000001
#define SENS_SAR1_EN_PAD_FORCE_S 31
-/* SENS_SAR1_EN_PAD : R/W; bitpos: [30:19]; default: 0; */
+/* SENS_SAR1_EN_PAD : RW; bitpos: [30:19]; default: 0;
+ * SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1
+ */
-#define SENS_SAR1_EN_PAD 0x000003ff
+#define SENS_SAR1_EN_PAD 0x00000fff
#define SENS_SAR1_EN_PAD_M (SENS_SAR1_EN_PAD_V << SENS_SAR1_EN_PAD_S)
-#define SENS_SAR1_EN_PAD_V 0x3ff
+#define SENS_SAR1_EN_PAD_V 0x00000fff
#define SENS_SAR1_EN_PAD_S 19
-/* SENS_MEAS1_START_FORCE : R/W; bitpos: [18]; default: 0; */
+/* SENS_MEAS1_START_FORCE : RW; bitpos: [18]; default: 0;
+ * 1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 controller
+ * is started by ULP-coprocessor
+ */
#define SENS_MEAS1_START_FORCE (BIT(18))
-#define SENS_MEAS1_START_FORCE_M (SENS_MEAS1_START_FORCE_V << \
- SENS_MEAS1_START_FORCE_S)
-#define SENS_MEAS1_START_FORCE_V 0x1
+#define SENS_MEAS1_START_FORCE_M (SENS_MEAS1_START_FORCE_V <<
SENS_MEAS1_START_FORCE_S)
+#define SENS_MEAS1_START_FORCE_V 0x00000001
#define SENS_MEAS1_START_FORCE_S 18
-/* SENS_MEAS1_START_SAR : R/W; bitpos: [17]; default: 0; */
+/* SENS_MEAS1_START_SAR : RW; bitpos: [17]; default: 0;
+ * SAR ADC1 controller (in RTC) starts conversion only active when
+ * reg_meas1_start_force = 1
+ */
#define SENS_MEAS1_START_SAR (BIT(17))
-#define SENS_MEAS1_START_SAR_M (SENS_MEAS1_START_SAR_V << \
- SENS_MEAS1_START_SAR_S)
-#define SENS_MEAS1_START_SAR_V 0x1
+#define SENS_MEAS1_START_SAR_M (SENS_MEAS1_START_SAR_V <<
SENS_MEAS1_START_SAR_S)
+#define SENS_MEAS1_START_SAR_V 0x00000001
#define SENS_MEAS1_START_SAR_S 17
-/* SENS_MEAS1_DONE_SAR : RO; bitpos: [16]; default: 0; */
+/* SENS_MEAS1_DONE_SAR : R; bitpos: [16]; default: 0;
+ * SAR ADC1 conversion done indication
+ */
#define SENS_MEAS1_DONE_SAR (BIT(16))
-#define SENS_MEAS1_DONE_SAR_M (SENS_MEAS1_DONE_SAR_V << \
- SENS_MEAS1_DONE_SAR_S)
-#define SENS_MEAS1_DONE_SAR_V 0x1
+#define SENS_MEAS1_DONE_SAR_M (SENS_MEAS1_DONE_SAR_V << SENS_MEAS1_DONE_SAR_S)
+#define SENS_MEAS1_DONE_SAR_V 0x00000001
#define SENS_MEAS1_DONE_SAR_S 16
-/* SENS_MEAS1_DATA_SAR : RO; bitpos: [15:0]; default: 0; */
+/* SENS_MEAS1_DATA_SAR : R; bitpos: [15:0]; default: 0;
+ * SAR ADC1 data
+ */
#define SENS_MEAS1_DATA_SAR 0x0000ffff
-#define SENS_MEAS1_DATA_SAR_M (SENS_MEAS1_DATA_SAR_V << \
- SENS_MEAS1_DATA_SAR_S)
-#define SENS_MEAS1_DATA_SAR_V 0xffff
+#define SENS_MEAS1_DATA_SAR_M (SENS_MEAS1_DATA_SAR_V << SENS_MEAS1_DATA_SAR_S)
+#define SENS_MEAS1_DATA_SAR_V 0x0000ffff
#define SENS_MEAS1_DATA_SAR_S 0
/* SENS_SAR_TOUCH_CTRL1_REG register */
#define SENS_SAR_TOUCH_CTRL1_REG (DR_REG_SENS_BASE + 0x58)
-/* SENS_HALL_PHASE_FORCE : R/W; bitpos: [27]; default: 0; */
+/* SENS_HALL_PHASE_FORCE : RW; bitpos: [27]; default: 0;
+ * 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in
+ * ULP-coprocessor
+ */
#define SENS_HALL_PHASE_FORCE (BIT(27))
-#define SENS_HALL_PHASE_FORCE_M (SENS_HALL_PHASE_FORCE_V << \
- SENS_HALL_PHASE_FORCE_S)
-#define SENS_HALL_PHASE_FORCE_V 0x1
+#define SENS_HALL_PHASE_FORCE_M (SENS_HALL_PHASE_FORCE_V <<
SENS_HALL_PHASE_FORCE_S)
+#define SENS_HALL_PHASE_FORCE_V 0x00000001
#define SENS_HALL_PHASE_FORCE_S 27
-/* SENS_XPD_HALL_FORCE : R/W; bitpos: [26]; default: 0; */
+/* SENS_XPD_HALL_FORCE : RW; bitpos: [26]; default: 0;
+ * 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in
+ * ULP-coprocessor
+ */
#define SENS_XPD_HALL_FORCE (BIT(26))
-#define SENS_XPD_HALL_FORCE_M (SENS_XPD_HALL_FORCE_V << \
- SENS_XPD_HALL_FORCE_S)
-#define SENS_XPD_HALL_FORCE_V 0x1
+#define SENS_XPD_HALL_FORCE_M (SENS_XPD_HALL_FORCE_V << SENS_XPD_HALL_FORCE_S)
+#define SENS_XPD_HALL_FORCE_V 0x00000001
#define SENS_XPD_HALL_FORCE_S 26
-/* SENS_TOUCH_OUT_1EN : R/W; bitpos: [25]; default: 1; */
+/* SENS_TOUCH_OUT_1EN : RW; bitpos: [25]; default: 1;
+ * 1: wakeup interrupt is generated if SET1 is "touched" 0: wakeup
+ * interrupt is generated only if SET1 & SET2 is both "touched"
+ */
#define SENS_TOUCH_OUT_1EN (BIT(25))
#define SENS_TOUCH_OUT_1EN_M (SENS_TOUCH_OUT_1EN_V << SENS_TOUCH_OUT_1EN_S)
-#define SENS_TOUCH_OUT_1EN_V 0x1
+#define SENS_TOUCH_OUT_1EN_V 0x00000001
#define SENS_TOUCH_OUT_1EN_S 25
-/* SENS_TOUCH_OUT_SEL : R/W; bitpos: [24]; default: 0; */
+/* SENS_TOUCH_OUT_SEL : RW; bitpos: [24]; default: 0;
+ * 1: when the counter is greater then the threshold the touch pad is
+ * considered as "touched" 0: when the counter is less than the threshold
+ * the touch pad is considered as "touched"
+ */
#define SENS_TOUCH_OUT_SEL (BIT(24))
#define SENS_TOUCH_OUT_SEL_M (SENS_TOUCH_OUT_SEL_V << SENS_TOUCH_OUT_SEL_S)
-#define SENS_TOUCH_OUT_SEL_V 0x1
+#define SENS_TOUCH_OUT_SEL_V 0x00000001
#define SENS_TOUCH_OUT_SEL_S 24
-/* SENS_TOUCH_XPD_WAIT : R/W; bitpos: [23:16]; default: 4; */
+/* SENS_TOUCH_XPD_WAIT : RW; bitpos: [23:16]; default: 4;
+ * the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
+ */
#define SENS_TOUCH_XPD_WAIT 0x000000ff
-#define SENS_TOUCH_XPD_WAIT_M (SENS_TOUCH_XPD_WAIT_V << \
- SENS_TOUCH_XPD_WAIT_S)
-#define SENS_TOUCH_XPD_WAIT_V 0xff
+#define SENS_TOUCH_XPD_WAIT_M (SENS_TOUCH_XPD_WAIT_V << SENS_TOUCH_XPD_WAIT_S)
+#define SENS_TOUCH_XPD_WAIT_V 0x000000ff
#define SENS_TOUCH_XPD_WAIT_S 16
-/* SENS_TOUCH_MEAS_DELAY : R/W; bitpos: [15:0]; default: 0x1000; */
+/* SENS_TOUCH_MEAS_DELAY : RW; bitpos: [15:0]; default: 4096;
+ * the meas length (in 8MHz)
+ */
#define SENS_TOUCH_MEAS_DELAY 0x0000ffff
-#define SENS_TOUCH_MEAS_DELAY_M (SENS_TOUCH_MEAS_DELAY_V << \
- SENS_TOUCH_MEAS_DELAY_S)
-#define SENS_TOUCH_MEAS_DELAY_V 0xffff
+#define SENS_TOUCH_MEAS_DELAY_M (SENS_TOUCH_MEAS_DELAY_V <<
SENS_TOUCH_MEAS_DELAY_S)
+#define SENS_TOUCH_MEAS_DELAY_V 0x0000ffff
#define SENS_TOUCH_MEAS_DELAY_S 0
/* SENS_SAR_TOUCH_THRES1_REG register */
#define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x5c)
-/* SENS_TOUCH_OUT_TH0 : R/W; bitpos: [31:16]; default: 0; */
+/* SENS_TOUCH_OUT_TH0 : RW; bitpos: [31:16]; default: 0;
+ * the threshold for touch pad 0
+ */
#define SENS_TOUCH_OUT_TH0 0x0000ffff
#define SENS_TOUCH_OUT_TH0_M (SENS_TOUCH_OUT_TH0_V << SENS_TOUCH_OUT_TH0_S)
-#define SENS_TOUCH_OUT_TH0_V 0xffff
+#define SENS_TOUCH_OUT_TH0_V 0x0000ffff
#define SENS_TOUCH_OUT_TH0_S 16
-/* SENS_TOUCH_OUT_TH1 : R/W; bitpos: [15:0]; default: 0; */
+/* SENS_TOUCH_OUT_TH1 : RW; bitpos: [15:0]; default: 0;
+ * the threshold for touch pad 1
+ */
#define SENS_TOUCH_OUT_TH1 0x0000ffff
#define SENS_TOUCH_OUT_TH1_M (SENS_TOUCH_OUT_TH1_V << SENS_TOUCH_OUT_TH1_S)
-#define SENS_TOUCH_OUT_TH1_V 0xffff
+#define SENS_TOUCH_OUT_TH1_V 0x0000ffff
#define SENS_TOUCH_OUT_TH1_S 0
/* SENS_SAR_TOUCH_THRES2_REG register */
#define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x60)
-/* SENS_TOUCH_OUT_TH2 : R/W; bitpos: [31:16]; default: 0; */
+/* SENS_TOUCH_OUT_TH2 : RW; bitpos: [31:16]; default: 0;
+ * the threshold for touch pad 2
+ */
#define SENS_TOUCH_OUT_TH2 0x0000ffff
#define SENS_TOUCH_OUT_TH2_M (SENS_TOUCH_OUT_TH2_V << SENS_TOUCH_OUT_TH2_S)
-#define SENS_TOUCH_OUT_TH2_V 0xffff
+#define SENS_TOUCH_OUT_TH2_V 0x0000ffff
#define SENS_TOUCH_OUT_TH2_S 16
-/* SENS_TOUCH_OUT_TH3 : R/W; bitpos: [15:0]; default: 0; */
+/* SENS_TOUCH_OUT_TH3 : RW; bitpos: [15:0]; default: 0;
+ * the threshold for touch pad 3
+ */
#define SENS_TOUCH_OUT_TH3 0x0000ffff
#define SENS_TOUCH_OUT_TH3_M (SENS_TOUCH_OUT_TH3_V << SENS_TOUCH_OUT_TH3_S)
-#define SENS_TOUCH_OUT_TH3_V 0xffff
+#define SENS_TOUCH_OUT_TH3_V 0x0000ffff
#define SENS_TOUCH_OUT_TH3_S 0
/* SENS_SAR_TOUCH_THRES3_REG register */
#define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x64)
-/* SENS_TOUCH_OUT_TH4 : R/W; bitpos: [31:16]; default: 0; */
+/* SENS_TOUCH_OUT_TH4 : RW; bitpos: [31:16]; default: 0;
+ * the threshold for touch pad 4
+ */
#define SENS_TOUCH_OUT_TH4 0x0000ffff
#define SENS_TOUCH_OUT_TH4_M (SENS_TOUCH_OUT_TH4_V << SENS_TOUCH_OUT_TH4_S)
-#define SENS_TOUCH_OUT_TH4_V 0xffff
+#define SENS_TOUCH_OUT_TH4_V 0x0000ffff
#define SENS_TOUCH_OUT_TH4_S 16
-/* SENS_TOUCH_OUT_TH5 : R/W; bitpos: [15:0]; default: 0; */
+/* SENS_TOUCH_OUT_TH5 : RW; bitpos: [15:0]; default: 0;
+ * the threshold for touch pad 5
+ */
#define SENS_TOUCH_OUT_TH5 0x0000ffff
#define SENS_TOUCH_OUT_TH5_M (SENS_TOUCH_OUT_TH5_V << SENS_TOUCH_OUT_TH5_S)
-#define SENS_TOUCH_OUT_TH5_V 0xffff
+#define SENS_TOUCH_OUT_TH5_V 0x0000ffff
#define SENS_TOUCH_OUT_TH5_S 0
/* SENS_SAR_TOUCH_THRES4_REG register */
#define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x68)
-/* SENS_TOUCH_OUT_TH6 : R/W; bitpos: [31:16]; default: 0; */
+/* SENS_TOUCH_OUT_TH6 : RW; bitpos: [31:16]; default: 0;
+ * the threshold for touch pad 6
+ */
#define SENS_TOUCH_OUT_TH6 0x0000ffff
#define SENS_TOUCH_OUT_TH6_M (SENS_TOUCH_OUT_TH6_V << SENS_TOUCH_OUT_TH6_S)
-#define SENS_TOUCH_OUT_TH6_V 0xffff
+#define SENS_TOUCH_OUT_TH6_V 0x0000ffff
#define SENS_TOUCH_OUT_TH6_S 16
-/* SENS_TOUCH_OUT_TH7 : R/W; bitpos: [15:0]; default: 0; */
+/* SENS_TOUCH_OUT_TH7 : RW; bitpos: [15:0]; default: 0;
+ * the threshold for touch pad 7
+ */
#define SENS_TOUCH_OUT_TH7 0x0000ffff
#define SENS_TOUCH_OUT_TH7_M (SENS_TOUCH_OUT_TH7_V << SENS_TOUCH_OUT_TH7_S)
-#define SENS_TOUCH_OUT_TH7_V 0xffff
+#define SENS_TOUCH_OUT_TH7_V 0x0000ffff
#define SENS_TOUCH_OUT_TH7_S 0
/* SENS_SAR_TOUCH_THRES5_REG register */
#define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x6c)
-/* SENS_TOUCH_OUT_TH8 : R/W; bitpos: [31:16]; default: 0; */
+/* SENS_TOUCH_OUT_TH8 : RW; bitpos: [31:16]; default: 0;
+ * the threshold for touch pad 8
+ */
#define SENS_TOUCH_OUT_TH8 0x0000ffff
#define SENS_TOUCH_OUT_TH8_M (SENS_TOUCH_OUT_TH8_V << SENS_TOUCH_OUT_TH8_S)
-#define SENS_TOUCH_OUT_TH8_V 0xffff
+#define SENS_TOUCH_OUT_TH8_V 0x0000ffff
#define SENS_TOUCH_OUT_TH8_S 16
-/* SENS_TOUCH_OUT_TH9 : R/W; bitpos: [15:0]; default: 0; */
+/* SENS_TOUCH_OUT_TH9 : RW; bitpos: [15:0]; default: 0;
+ * the threshold for touch pad 9
+ */
#define SENS_TOUCH_OUT_TH9 0x0000ffff
#define SENS_TOUCH_OUT_TH9_M (SENS_TOUCH_OUT_TH9_V << SENS_TOUCH_OUT_TH9_S)
-#define SENS_TOUCH_OUT_TH9_V 0xffff
+#define SENS_TOUCH_OUT_TH9_V 0x0000ffff
#define SENS_TOUCH_OUT_TH9_S 0
/* SENS_SAR_TOUCH_OUT1_REG register */
#define SENS_SAR_TOUCH_OUT1_REG (DR_REG_SENS_BASE + 0x70)
-/* SENS_TOUCH_MEAS_OUT0 : RO; bitpos: [31:16]; default: 0; */
+/* SENS_TOUCH_MEAS_OUT0 : R; bitpos: [31:16]; default: 0;
+ * the counter for touch pad 0
+ */
#define SENS_TOUCH_MEAS_OUT0 0x0000ffff
-#define SENS_TOUCH_MEAS_OUT0_M (SENS_TOUCH_MEAS_OUT0_V << \
- SENS_TOUCH_MEAS_OUT0_S)
-#define SENS_TOUCH_MEAS_OUT0_V 0xffff
+#define SENS_TOUCH_MEAS_OUT0_M (SENS_TOUCH_MEAS_OUT0_V <<
SENS_TOUCH_MEAS_OUT0_S)
+#define SENS_TOUCH_MEAS_OUT0_V 0x0000ffff
#define SENS_TOUCH_MEAS_OUT0_S 16
-/* SENS_TOUCH_MEAS_OUT1 : RO; bitpos: [15:0]; default: 0; */
+/* SENS_TOUCH_MEAS_OUT1 : R; bitpos: [15:0]; default: 0;
+ * the counter for touch pad 1
+ */
#define SENS_TOUCH_MEAS_OUT1 0x0000ffff
-#define SENS_TOUCH_MEAS_OUT1_M (SENS_TOUCH_MEAS_OUT1_V << \
- SENS_TOUCH_MEAS_OUT1_S)
-#define SENS_TOUCH_MEAS_OUT1_V 0xffff
+#define SENS_TOUCH_MEAS_OUT1_M (SENS_TOUCH_MEAS_OUT1_V <<
SENS_TOUCH_MEAS_OUT1_S)
+#define SENS_TOUCH_MEAS_OUT1_V 0x0000ffff
#define SENS_TOUCH_MEAS_OUT1_S 0
/* SENS_SAR_TOUCH_OUT2_REG register */
#define SENS_SAR_TOUCH_OUT2_REG (DR_REG_SENS_BASE + 0x74)
-/* SENS_TOUCH_MEAS_OUT2 : RO; bitpos: [31:16]; default: 0; */
+/* SENS_TOUCH_MEAS_OUT2 : R; bitpos: [31:16]; default: 0;
+ * the counter for touch pad 2
+ */
#define SENS_TOUCH_MEAS_OUT2 0x0000ffff
-#define SENS_TOUCH_MEAS_OUT2_M (SENS_TOUCH_MEAS_OUT2_V << \
- SENS_TOUCH_MEAS_OUT2_S)
-#define SENS_TOUCH_MEAS_OUT2_V 0xffff
+#define SENS_TOUCH_MEAS_OUT2_M (SENS_TOUCH_MEAS_OUT2_V <<
SENS_TOUCH_MEAS_OUT2_S)
+#define SENS_TOUCH_MEAS_OUT2_V 0x0000ffff
#define SENS_TOUCH_MEAS_OUT2_S 16
-/* SENS_TOUCH_MEAS_OUT3 : RO; bitpos: [15:0]; default: 0; */
+/* SENS_TOUCH_MEAS_OUT3 : R; bitpos: [15:0]; default: 0;
+ * the counter for touch pad 3
+ */
#define SENS_TOUCH_MEAS_OUT3 0x0000ffff
-#define SENS_TOUCH_MEAS_OUT3_M (SENS_TOUCH_MEAS_OUT3_V << \
- SENS_TOUCH_MEAS_OUT3_S)
-#define SENS_TOUCH_MEAS_OUT3_V 0xffff
+#define SENS_TOUCH_MEAS_OUT3_M (SENS_TOUCH_MEAS_OUT3_V <<
SENS_TOUCH_MEAS_OUT3_S)
+#define SENS_TOUCH_MEAS_OUT3_V 0x0000ffff
#define SENS_TOUCH_MEAS_OUT3_S 0
/* SENS_SAR_TOUCH_OUT3_REG register */
#define SENS_SAR_TOUCH_OUT3_REG (DR_REG_SENS_BASE + 0x78)
-/* SENS_TOUCH_MEAS_OUT4 : RO; bitpos: [31:16]; default: 0; */
+/* SENS_TOUCH_MEAS_OUT4 : R; bitpos: [31:16]; default: 0;
+ * the counter for touch pad 4
+ */
#define SENS_TOUCH_MEAS_OUT4 0x0000ffff
-#define SENS_TOUCH_MEAS_OUT4_M (SENS_TOUCH_MEAS_OUT4_V << \
- SENS_TOUCH_MEAS_OUT4_S)
-#define SENS_TOUCH_MEAS_OUT4_V 0xffff
+#define SENS_TOUCH_MEAS_OUT4_M (SENS_TOUCH_MEAS_OUT4_V <<
SENS_TOUCH_MEAS_OUT4_S)
+#define SENS_TOUCH_MEAS_OUT4_V 0x0000ffff
#define SENS_TOUCH_MEAS_OUT4_S 16
-/* SENS_TOUCH_MEAS_OUT5 : RO; bitpos: [15:0]; default: 0; */
+/* SENS_TOUCH_MEAS_OUT5 : R; bitpos: [15:0]; default: 0;
+ * the counter for touch pad 5
+ */
#define SENS_TOUCH_MEAS_OUT5 0x0000ffff
-#define SENS_TOUCH_MEAS_OUT5_M (SENS_TOUCH_MEAS_OUT5_V << \
- SENS_TOUCH_MEAS_OUT5_S)
-#define SENS_TOUCH_MEAS_OUT5_V 0xffff
+#define SENS_TOUCH_MEAS_OUT5_M (SENS_TOUCH_MEAS_OUT5_V <<
SENS_TOUCH_MEAS_OUT5_S)
+#define SENS_TOUCH_MEAS_OUT5_V 0x0000ffff
#define SENS_TOUCH_MEAS_OUT5_S 0
/* SENS_SAR_TOUCH_OUT4_REG register */
#define SENS_SAR_TOUCH_OUT4_REG (DR_REG_SENS_BASE + 0x7c)
-/* SENS_TOUCH_MEAS_OUT6 : RO; bitpos: [31:16]; default: 0; */
+/* SENS_TOUCH_MEAS_OUT6 : R; bitpos: [31:16]; default: 0;
+ * the counter for touch pad 6
+ */
#define SENS_TOUCH_MEAS_OUT6 0x0000ffff
-#define SENS_TOUCH_MEAS_OUT6_M (SENS_TOUCH_MEAS_OUT6_V << \
- SENS_TOUCH_MEAS_OUT6_S)
-#define SENS_TOUCH_MEAS_OUT6_V 0xffff
+#define SENS_TOUCH_MEAS_OUT6_M (SENS_TOUCH_MEAS_OUT6_V <<
SENS_TOUCH_MEAS_OUT6_S)
+#define SENS_TOUCH_MEAS_OUT6_V 0x0000ffff
#define SENS_TOUCH_MEAS_OUT6_S 16
-/* SENS_TOUCH_MEAS_OUT7 : RO; bitpos: [15:0]; default: 0; */
+/* SENS_TOUCH_MEAS_OUT7 : R; bitpos: [15:0]; default: 0;
+ * the counter for touch pad 7
+ */
#define SENS_TOUCH_MEAS_OUT7 0x0000ffff
-#define SENS_TOUCH_MEAS_OUT7_M (SENS_TOUCH_MEAS_OUT7_V << \
- SENS_TOUCH_MEAS_OUT7_S)
-#define SENS_TOUCH_MEAS_OUT7_V 0xffff
+#define SENS_TOUCH_MEAS_OUT7_M (SENS_TOUCH_MEAS_OUT7_V <<
SENS_TOUCH_MEAS_OUT7_S)
+#define SENS_TOUCH_MEAS_OUT7_V 0x0000ffff
#define SENS_TOUCH_MEAS_OUT7_S 0
/* SENS_SAR_TOUCH_OUT5_REG register */
#define SENS_SAR_TOUCH_OUT5_REG (DR_REG_SENS_BASE + 0x80)
-/* SENS_TOUCH_MEAS_OUT8 : RO; bitpos: [31:16]; default: 0; */
+/* SENS_TOUCH_MEAS_OUT8 : R; bitpos: [31:16]; default: 0;
+ * the counter for touch pad 8
+ */
#define SENS_TOUCH_MEAS_OUT8 0x0000ffff
-#define SENS_TOUCH_MEAS_OUT8_M (SENS_TOUCH_MEAS_OUT8_V << \
- SENS_TOUCH_MEAS_OUT8_S)
-#define SENS_TOUCH_MEAS_OUT8_V 0xffff
+#define SENS_TOUCH_MEAS_OUT8_M (SENS_TOUCH_MEAS_OUT8_V <<
SENS_TOUCH_MEAS_OUT8_S)
+#define SENS_TOUCH_MEAS_OUT8_V 0x0000ffff
#define SENS_TOUCH_MEAS_OUT8_S 16
-/* SENS_TOUCH_MEAS_OUT9 : RO; bitpos: [15:0]; default: 0; */
+/* SENS_TOUCH_MEAS_OUT9 : R; bitpos: [15:0]; default: 0;
+ * the counter for touch pad 9
+ */
#define SENS_TOUCH_MEAS_OUT9 0x0000ffff
-#define SENS_TOUCH_MEAS_OUT9_M (SENS_TOUCH_MEAS_OUT9_V << \
- SENS_TOUCH_MEAS_OUT9_S)
-#define SENS_TOUCH_MEAS_OUT9_V 0xffff
+#define SENS_TOUCH_MEAS_OUT9_M (SENS_TOUCH_MEAS_OUT9_V <<
SENS_TOUCH_MEAS_OUT9_S)
+#define SENS_TOUCH_MEAS_OUT9_V 0x0000ffff
#define SENS_TOUCH_MEAS_OUT9_S 0
/* SENS_SAR_TOUCH_CTRL2_REG register */
#define SENS_SAR_TOUCH_CTRL2_REG (DR_REG_SENS_BASE + 0x84)
-/* SENS_TOUCH_MEAS_EN_CLR : WO; bitpos: [30]; default: 0; */
+/* SENS_TOUCH_MEAS_EN_CLR : W; bitpos: [30]; default: 0;
+ * to clear reg_touch_meas_en
+ */
#define SENS_TOUCH_MEAS_EN_CLR (BIT(30))
-#define SENS_TOUCH_MEAS_EN_CLR_M (SENS_TOUCH_MEAS_EN_CLR_V << \
- SENS_TOUCH_MEAS_EN_CLR_S)
-#define SENS_TOUCH_MEAS_EN_CLR_V 0x1
+#define SENS_TOUCH_MEAS_EN_CLR_M (SENS_TOUCH_MEAS_EN_CLR_V <<
SENS_TOUCH_MEAS_EN_CLR_S)
+#define SENS_TOUCH_MEAS_EN_CLR_V 0x00000001
#define SENS_TOUCH_MEAS_EN_CLR_S 30
-/* SENS_TOUCH_SLEEP_CYCLES : R/W; bitpos: [29:14]; default: 0x100; */
+/* SENS_TOUCH_SLEEP_CYCLES : RW; bitpos: [29:14]; default: 256;
+ * sleep cycles for timer
+ */
#define SENS_TOUCH_SLEEP_CYCLES 0x0000ffff
-#define SENS_TOUCH_SLEEP_CYCLES_M (SENS_TOUCH_SLEEP_CYCLES_V << \
- SENS_TOUCH_SLEEP_CYCLES_S)
-#define SENS_TOUCH_SLEEP_CYCLES_V 0xffff
+#define SENS_TOUCH_SLEEP_CYCLES_M (SENS_TOUCH_SLEEP_CYCLES_V <<
SENS_TOUCH_SLEEP_CYCLES_S)
+#define SENS_TOUCH_SLEEP_CYCLES_V 0x0000ffff
#define SENS_TOUCH_SLEEP_CYCLES_S 14
-/* SENS_TOUCH_START_FORCE : R/W; bitpos: [13]; default: 0; */
+/* SENS_TOUCH_START_FORCE : RW; bitpos: [13]; default: 0;
+ * 1: to start touch fsm by SW 0: to start touch fsm by timer
+ */
#define SENS_TOUCH_START_FORCE (BIT(13))
-#define SENS_TOUCH_START_FORCE_M (SENS_TOUCH_START_FORCE_V << \
- SENS_TOUCH_START_FORCE_S)
-#define SENS_TOUCH_START_FORCE_V 0x1
+#define SENS_TOUCH_START_FORCE_M (SENS_TOUCH_START_FORCE_V <<
SENS_TOUCH_START_FORCE_S)
+#define SENS_TOUCH_START_FORCE_V 0x00000001
#define SENS_TOUCH_START_FORCE_S 13
-/* SENS_TOUCH_START_EN : R/W; bitpos: [12]; default: 0; */
+/* SENS_TOUCH_START_EN : RW; bitpos: [12]; default: 0;
+ * 1: start touch fsm valid when reg_touch_start_force is set
+ */
#define SENS_TOUCH_START_EN (BIT(12))
-#define SENS_TOUCH_START_EN_M (SENS_TOUCH_START_EN_V << \
- SENS_TOUCH_START_EN_S)
-#define SENS_TOUCH_START_EN_V 0x1
+#define SENS_TOUCH_START_EN_M (SENS_TOUCH_START_EN_V << SENS_TOUCH_START_EN_S)
+#define SENS_TOUCH_START_EN_V 0x00000001
#define SENS_TOUCH_START_EN_S 12
-/* SENS_TOUCH_START_FSM_EN : R/W; bitpos: [11]; default: 1; */
+/* SENS_TOUCH_START_FSM_EN : RW; bitpos: [11]; default: 1;
+ * 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START &
+ * TOUCH_XPD is controlled by registers
+ */
#define SENS_TOUCH_START_FSM_EN (BIT(11))
-#define SENS_TOUCH_START_FSM_EN_M (SENS_TOUCH_START_FSM_EN_V << \
- SENS_TOUCH_START_FSM_EN_S)
-#define SENS_TOUCH_START_FSM_EN_V 0x1
+#define SENS_TOUCH_START_FSM_EN_M (SENS_TOUCH_START_FSM_EN_V <<
SENS_TOUCH_START_FSM_EN_S)
+#define SENS_TOUCH_START_FSM_EN_V 0x00000001
#define SENS_TOUCH_START_FSM_EN_S 11
-/* SENS_TOUCH_MEAS_DONE : RO; bitpos: [10]; default: 0; */
+/* SENS_TOUCH_MEAS_DONE : R; bitpos: [10]; default: 0;
+ * fsm set 1 to indicate touch touch meas is done
+ */
#define SENS_TOUCH_MEAS_DONE (BIT(10))
-#define SENS_TOUCH_MEAS_DONE_M (SENS_TOUCH_MEAS_DONE_V << \
- SENS_TOUCH_MEAS_DONE_S)
-#define SENS_TOUCH_MEAS_DONE_V 0x1
+#define SENS_TOUCH_MEAS_DONE_M (SENS_TOUCH_MEAS_DONE_V <<
SENS_TOUCH_MEAS_DONE_S)
+#define SENS_TOUCH_MEAS_DONE_V 0x00000001
#define SENS_TOUCH_MEAS_DONE_S 10
-/* SENS_TOUCH_MEAS_EN : RO; bitpos: [9:0]; default: 0; */
+/* SENS_TOUCH_MEAS_EN : R; bitpos: [9:0]; default: 0;
+ * 10-bit register to indicate which pads are "touched"
+ */
#define SENS_TOUCH_MEAS_EN 0x000003ff
#define SENS_TOUCH_MEAS_EN_M (SENS_TOUCH_MEAS_EN_V << SENS_TOUCH_MEAS_EN_S)
-#define SENS_TOUCH_MEAS_EN_V 0x3ff
+#define SENS_TOUCH_MEAS_EN_V 0x000003ff
#define SENS_TOUCH_MEAS_EN_S 0
/* SENS_SAR_TOUCH_ENABLE_REG register */
#define SENS_SAR_TOUCH_ENABLE_REG (DR_REG_SENS_BASE + 0x8c)
-/* SENS_TOUCH_PAD_OUTEN1 : R/W; bitpos: [29:20]; default: 0x3ff; */
+/* SENS_TOUCH_PAD_OUTEN1 : RW; bitpos: [29:20]; default: 1023;
+ * Bitmap defining SET1 for generating wakeup interrupt. SET1 is "touched"
+ * only if at least one of touch pad in SET1 is "touched".
+ */
#define SENS_TOUCH_PAD_OUTEN1 0x000003ff
-#define SENS_TOUCH_PAD_OUTEN1_M (SENS_TOUCH_PAD_OUTEN1_V << \
- SENS_TOUCH_PAD_OUTEN1_S)
-#define SENS_TOUCH_PAD_OUTEN1_V 0x3ff
+#define SENS_TOUCH_PAD_OUTEN1_M (SENS_TOUCH_PAD_OUTEN1_V <<
SENS_TOUCH_PAD_OUTEN1_S)
+#define SENS_TOUCH_PAD_OUTEN1_V 0x000003ff
#define SENS_TOUCH_PAD_OUTEN1_S 20
-/* SENS_TOUCH_PAD_OUTEN2 : R/W; bitpos: [19:10]; default: 0x3ff; */
+/* SENS_TOUCH_PAD_OUTEN2 : RW; bitpos: [19:10]; default: 1023;
+ * Bitmap defining SET2 for generating wakeup interrupt. SET2 is "touched"
+ * only if at least one of touch pad in SET2 is "touched".
+ */
#define SENS_TOUCH_PAD_OUTEN2 0x000003ff
-#define SENS_TOUCH_PAD_OUTEN2_M (SENS_TOUCH_PAD_OUTEN2_V << \
- SENS_TOUCH_PAD_OUTEN2_S)
-#define SENS_TOUCH_PAD_OUTEN2_V 0x3ff
+#define SENS_TOUCH_PAD_OUTEN2_M (SENS_TOUCH_PAD_OUTEN2_V <<
SENS_TOUCH_PAD_OUTEN2_S)
+#define SENS_TOUCH_PAD_OUTEN2_V 0x000003ff
#define SENS_TOUCH_PAD_OUTEN2_S 10
-/* SENS_TOUCH_PAD_WORKEN : R/W; bitpos: [9:0]; default: 0x3ff; */
+/* SENS_TOUCH_PAD_WORKEN : RW; bitpos: [9:0]; default: 1023;
+ * Bitmap defining the working set during the measurement.
+ */
#define SENS_TOUCH_PAD_WORKEN 0x000003ff
-#define SENS_TOUCH_PAD_WORKEN_M (SENS_TOUCH_PAD_WORKEN_V << \
- SENS_TOUCH_PAD_WORKEN_S)
-#define SENS_TOUCH_PAD_WORKEN_V 0x3ff
+#define SENS_TOUCH_PAD_WORKEN_M (SENS_TOUCH_PAD_WORKEN_V <<
SENS_TOUCH_PAD_WORKEN_S)
+#define SENS_TOUCH_PAD_WORKEN_V 0x000003ff
#define SENS_TOUCH_PAD_WORKEN_S 0
/* SENS_SAR_READ_CTRL2_REG register */
#define SENS_SAR_READ_CTRL2_REG (DR_REG_SENS_BASE + 0x90)
-/* SENS_SAR2_DATA_INV : R/W; bitpos: [29]; default: 0; */
+/* SENS_SAR2_DATA_INV : RW; bitpos: [29]; default: 0;
+ * Invert SAR ADC2 data
+ */
#define SENS_SAR2_DATA_INV (BIT(29))
#define SENS_SAR2_DATA_INV_M (SENS_SAR2_DATA_INV_V << SENS_SAR2_DATA_INV_S)
-#define SENS_SAR2_DATA_INV_V 0x1
+#define SENS_SAR2_DATA_INV_V 0x00000001
#define SENS_SAR2_DATA_INV_S 29
-/* SENS_SAR2_DIG_FORCE : R/W; bitpos: [28]; default: 0; */
+/* SENS_SAR2_DIG_FORCE : RW; bitpos: [28]; default: 0;
+ * 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2
+ * controlled by RTC ADC2 CTRL
+ */
#define SENS_SAR2_DIG_FORCE (BIT(28))
-#define SENS_SAR2_DIG_FORCE_M (SENS_SAR2_DIG_FORCE_V << \
- SENS_SAR2_DIG_FORCE_S)
-#define SENS_SAR2_DIG_FORCE_V 0x1
+#define SENS_SAR2_DIG_FORCE_M (SENS_SAR2_DIG_FORCE_V << SENS_SAR2_DIG_FORCE_S)
+#define SENS_SAR2_DIG_FORCE_V 0x00000001
#define SENS_SAR2_DIG_FORCE_S 28
-/* SENS_SAR2_SAMPLE_BIT : R/W; bitpos: [17:16]; default: 3; */
+/* SENS_SAR2_PWDET_FORCE : RW; bitpos: [27]; default: 0; */
+
+#define SENS_SAR2_PWDET_FORCE (BIT(27))
+#define SENS_SAR2_PWDET_FORCE_M (SENS_SAR2_PWDET_FORCE_V <<
SENS_SAR2_PWDET_FORCE_S)
+#define SENS_SAR2_PWDET_FORCE_V 0x00000001
+#define SENS_SAR2_PWDET_FORCE_S 27
+
+/* SENS_SAR2_SAMPLE_NUM : RW; bitpos: [26:19]; default: 0; */
+
+#define SENS_SAR2_SAMPLE_NUM 0x000000ff
+#define SENS_SAR2_SAMPLE_NUM_M (SENS_SAR2_SAMPLE_NUM_V <<
SENS_SAR2_SAMPLE_NUM_S)
+#define SENS_SAR2_SAMPLE_NUM_V 0x000000ff
+#define SENS_SAR2_SAMPLE_NUM_S 19
+
+/* SENS_SAR2_CLK_GATED : RW; bitpos: [18]; default: 1; */
+
+#define SENS_SAR2_CLK_GATED (BIT(18))
+#define SENS_SAR2_CLK_GATED_M (SENS_SAR2_CLK_GATED_V << SENS_SAR2_CLK_GATED_S)
+#define SENS_SAR2_CLK_GATED_V 0x00000001
+#define SENS_SAR2_CLK_GATED_S 18
+
+/* SENS_SAR2_SAMPLE_BIT : RW; bitpos: [17:16]; default: 3;
+ * 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for
+ * 12-bit width
+ */
#define SENS_SAR2_SAMPLE_BIT 0x00000003
-#define SENS_SAR2_SAMPLE_BIT_M (SENS_SAR2_SAMPLE_BIT_V << \
- SENS_SAR2_SAMPLE_BIT_S)
-#define SENS_SAR2_SAMPLE_BIT_V 0x3
+#define SENS_SAR2_SAMPLE_BIT_M (SENS_SAR2_SAMPLE_BIT_V <<
SENS_SAR2_SAMPLE_BIT_S)
+#define SENS_SAR2_SAMPLE_BIT_V 0x00000003
#define SENS_SAR2_SAMPLE_BIT_S 16
-/* SENS_SAR2_SAMPLE_CYCLE : R/W; bitpos: [15:8]; default: 9; */
+/* SENS_SAR2_SAMPLE_CYCLE : RW; bitpos: [15:8]; default: 9;
+ * sample cycles for SAR ADC2
+ */
#define SENS_SAR2_SAMPLE_CYCLE 0x000000ff
-#define SENS_SAR2_SAMPLE_CYCLE_M (SENS_SAR2_SAMPLE_CYCLE_V << \
- SENS_SAR2_SAMPLE_CYCLE_S)
-#define SENS_SAR2_SAMPLE_CYCLE_V 0xff
+#define SENS_SAR2_SAMPLE_CYCLE_M (SENS_SAR2_SAMPLE_CYCLE_V <<
SENS_SAR2_SAMPLE_CYCLE_S)
+#define SENS_SAR2_SAMPLE_CYCLE_V 0x000000ff
#define SENS_SAR2_SAMPLE_CYCLE_S 8
-/* SENS_SAR2_CLK_DIV : R/W; bitpos: [7:0]; default: 2; */
+/* SENS_SAR2_CLK_DIV : RW; bitpos: [7:0]; default: 2;
+ * clock divider
+ */
#define SENS_SAR2_CLK_DIV 0x000000ff
#define SENS_SAR2_CLK_DIV_M (SENS_SAR2_CLK_DIV_V << SENS_SAR2_CLK_DIV_S)
-#define SENS_SAR2_CLK_DIV_V 0xff
+#define SENS_SAR2_CLK_DIV_V 0x000000ff
#define SENS_SAR2_CLK_DIV_S 0
/* SENS_SAR_MEAS_START2_REG register */
#define SENS_SAR_MEAS_START2_REG (DR_REG_SENS_BASE + 0x94)
-/* SENS_SAR2_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0; */
+/* SENS_SAR2_EN_PAD_FORCE : RW; bitpos: [31]; default: 0;
+ * 1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 pad enable
+ * bitmap is controlled by ULP-coprocessor
+ */
#define SENS_SAR2_EN_PAD_FORCE (BIT(31))
-#define SENS_SAR2_EN_PAD_FORCE_M (SENS_SAR2_EN_PAD_FORCE_V << \
- SENS_SAR2_EN_PAD_FORCE_S)
-#define SENS_SAR2_EN_PAD_FORCE_V 0x1
+#define SENS_SAR2_EN_PAD_FORCE_M (SENS_SAR2_EN_PAD_FORCE_V <<
SENS_SAR2_EN_PAD_FORCE_S)
+#define SENS_SAR2_EN_PAD_FORCE_V 0x00000001
#define SENS_SAR2_EN_PAD_FORCE_S 31
-/* SENS_SAR2_EN_PAD : R/W; bitpos: [30:19]; default: 0; */
+/* SENS_SAR2_EN_PAD : RW; bitpos: [30:19]; default: 0;
+ * SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1
+ */
-#define SENS_SAR2_EN_PAD 0x000003ff
+#define SENS_SAR2_EN_PAD 0x00000fff
#define SENS_SAR2_EN_PAD_M (SENS_SAR2_EN_PAD_V << SENS_SAR2_EN_PAD_S)
-#define SENS_SAR2_EN_PAD_V 0x3ff
+#define SENS_SAR2_EN_PAD_V 0x00000fff
#define SENS_SAR2_EN_PAD_S 19
-/* SENS_MEAS2_START_FORCE : R/W; bitpos: [18]; default: 0; */
+/* SENS_MEAS2_START_FORCE : RW; bitpos: [18]; default: 0;
+ * 1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 controller
+ * is started by ULP-coprocessor
+ */
#define SENS_MEAS2_START_FORCE (BIT(18))
-#define SENS_MEAS2_START_FORCE_M (SENS_MEAS2_START_FORCE_V << \
- SENS_MEAS2_START_FORCE_S)
-#define SENS_MEAS2_START_FORCE_V 0x1
+#define SENS_MEAS2_START_FORCE_M (SENS_MEAS2_START_FORCE_V <<
SENS_MEAS2_START_FORCE_S)
+#define SENS_MEAS2_START_FORCE_V 0x00000001
#define SENS_MEAS2_START_FORCE_S 18
-/* SENS_MEAS2_START_SAR : R/W; bitpos: [17]; default: 0; */
+/* SENS_MEAS2_START_SAR : RW; bitpos: [17]; default: 0;
+ * SAR ADC2 controller (in RTC) starts conversion only active when
+ * reg_meas2_start_force = 1
+ */
#define SENS_MEAS2_START_SAR (BIT(17))
-#define SENS_MEAS2_START_SAR_M (SENS_MEAS2_START_SAR_V << \
- SENS_MEAS2_START_SAR_S)
-#define SENS_MEAS2_START_SAR_V 0x1
+#define SENS_MEAS2_START_SAR_M (SENS_MEAS2_START_SAR_V <<
SENS_MEAS2_START_SAR_S)
+#define SENS_MEAS2_START_SAR_V 0x00000001
#define SENS_MEAS2_START_SAR_S 17
-/* SENS_MEAS2_DONE_SAR : RO; bitpos: [16]; default: 0; */
+/* SENS_MEAS2_DONE_SAR : R; bitpos: [16]; default: 0;
+ * SAR ADC2 conversion done indication
+ */
#define SENS_MEAS2_DONE_SAR (BIT(16))
-#define SENS_MEAS2_DONE_SAR_M (SENS_MEAS2_DONE_SAR_V << \
- SENS_MEAS2_DONE_SAR_S)
-#define SENS_MEAS2_DONE_SAR_V 0x1
+#define SENS_MEAS2_DONE_SAR_M (SENS_MEAS2_DONE_SAR_V << SENS_MEAS2_DONE_SAR_S)
+#define SENS_MEAS2_DONE_SAR_V 0x00000001
#define SENS_MEAS2_DONE_SAR_S 16
-/* SENS_MEAS2_DATA_SAR : RO; bitpos: [15:0]; default: 0; */
+/* SENS_MEAS2_DATA_SAR : R; bitpos: [15:0]; default: 0;
+ * SAR ADC2 data
+ */
#define SENS_MEAS2_DATA_SAR 0x0000ffff
-#define SENS_MEAS2_DATA_SAR_M (SENS_MEAS2_DATA_SAR_V << \
- SENS_MEAS2_DATA_SAR_S)
-#define SENS_MEAS2_DATA_SAR_V 0xffff
+#define SENS_MEAS2_DATA_SAR_M (SENS_MEAS2_DATA_SAR_V << SENS_MEAS2_DATA_SAR_S)
+#define SENS_MEAS2_DATA_SAR_V 0x0000ffff
#define SENS_MEAS2_DATA_SAR_S 0
/* SENS_SAR_DAC_CTRL1_REG register */
#define SENS_SAR_DAC_CTRL1_REG (DR_REG_SENS_BASE + 0x98)
-/* SENS_DAC_CLK_INV : R/W; bitpos: [25]; default: 0; */
+/* SENS_DAC_CLK_INV : RW; bitpos: [25]; default: 0;
+ * 1: invert PDAC_CLK
+ */
#define SENS_DAC_CLK_INV (BIT(25))
#define SENS_DAC_CLK_INV_M (SENS_DAC_CLK_INV_V << SENS_DAC_CLK_INV_S)
-#define SENS_DAC_CLK_INV_V 0x1
+#define SENS_DAC_CLK_INV_V 0x00000001
#define SENS_DAC_CLK_INV_S 25
-/* SENS_DAC_CLK_FORCE_HIGH : R/W; bitpos: [24]; default: 0; */
+/* SENS_DAC_CLK_FORCE_HIGH : RW; bitpos: [24]; default: 0;
+ * 1: force PDAC_CLK to high
+ */
#define SENS_DAC_CLK_FORCE_HIGH (BIT(24))
-#define SENS_DAC_CLK_FORCE_HIGH_M (SENS_DAC_CLK_FORCE_HIGH_V << \
- SENS_DAC_CLK_FORCE_HIGH_S)
-#define SENS_DAC_CLK_FORCE_HIGH_V 0x1
+#define SENS_DAC_CLK_FORCE_HIGH_M (SENS_DAC_CLK_FORCE_HIGH_V <<
SENS_DAC_CLK_FORCE_HIGH_S)
+#define SENS_DAC_CLK_FORCE_HIGH_V 0x00000001
#define SENS_DAC_CLK_FORCE_HIGH_S 24
-/* SENS_DAC_CLK_FORCE_LOW : R/W; bitpos: [23]; default: 0; */
+/* SENS_DAC_CLK_FORCE_LOW : RW; bitpos: [23]; default: 0;
+ * 1: force PDAC_CLK to low
+ */
#define SENS_DAC_CLK_FORCE_LOW (BIT(23))
-#define SENS_DAC_CLK_FORCE_LOW_M (SENS_DAC_CLK_FORCE_LOW_V << \
- SENS_DAC_CLK_FORCE_LOW_S)
-#define SENS_DAC_CLK_FORCE_LOW_V 0x1
+#define SENS_DAC_CLK_FORCE_LOW_M (SENS_DAC_CLK_FORCE_LOW_V <<
SENS_DAC_CLK_FORCE_LOW_S)
+#define SENS_DAC_CLK_FORCE_LOW_V 0x00000001
#define SENS_DAC_CLK_FORCE_LOW_S 23
-/* SENS_DAC_DIG_FORCE : R/W; bitpos: [22]; default: 0; */
+/* SENS_DAC_DIG_FORCE : RW; bitpos: [22]; default: 0;
+ * 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA
+ */
#define SENS_DAC_DIG_FORCE (BIT(22))
#define SENS_DAC_DIG_FORCE_M (SENS_DAC_DIG_FORCE_V << SENS_DAC_DIG_FORCE_S)
-#define SENS_DAC_DIG_FORCE_V 0x1
+#define SENS_DAC_DIG_FORCE_V 0x00000001
#define SENS_DAC_DIG_FORCE_S 22
-/* SENS_SW_TONE_EN : R/W; bitpos: [16]; default: 0; */
+/* SENS_DEBUG_BIT_SEL : RW; bitpos: [21:17]; default: 0; */
+
+#define SENS_DEBUG_BIT_SEL 0x0000001f
+#define SENS_DEBUG_BIT_SEL_M (SENS_DEBUG_BIT_SEL_V << SENS_DEBUG_BIT_SEL_S)
+#define SENS_DEBUG_BIT_SEL_V 0x0000001f
+#define SENS_DEBUG_BIT_SEL_S 17
+
+/* SENS_SW_TONE_EN : RW; bitpos: [16]; default: 0;
+ * 1: enable CW generator 0: disable CW generator
+ */
#define SENS_SW_TONE_EN (BIT(16))
#define SENS_SW_TONE_EN_M (SENS_SW_TONE_EN_V << SENS_SW_TONE_EN_S)
-#define SENS_SW_TONE_EN_V 0x1
+#define SENS_SW_TONE_EN_V 0x00000001
#define SENS_SW_TONE_EN_S 16
-/* SENS_SW_FSTEP : R/W; bitpos: [15:0]; default: 0; */
+/* SENS_SW_FSTEP : RW; bitpos: [15:0]; default: 0;
+ * frequency step for CW generator can be used to adjust the frequency
+ */
#define SENS_SW_FSTEP 0x0000ffff
#define SENS_SW_FSTEP_M (SENS_SW_FSTEP_V << SENS_SW_FSTEP_S)
-#define SENS_SW_FSTEP_V 0xffff
+#define SENS_SW_FSTEP_V 0x0000ffff
#define SENS_SW_FSTEP_S 0
/* SENS_SAR_DAC_CTRL2_REG register */
#define SENS_SAR_DAC_CTRL2_REG (DR_REG_SENS_BASE + 0x9c)
-/* SENS_DAC_CW_EN2 : R/W; bitpos: [25]; default: 1; */
+/* SENS_DAC_CW_EN2 : RW; bitpos: [25]; default: 1;
+ * 1: to select CW generator as source to PDAC2_DAC[7:0] 0: to select
+ * register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]
+ */
#define SENS_DAC_CW_EN2 (BIT(25))
#define SENS_DAC_CW_EN2_M (SENS_DAC_CW_EN2_V << SENS_DAC_CW_EN2_S)
-#define SENS_DAC_CW_EN2_V 0x1
+#define SENS_DAC_CW_EN2_V 0x00000001
#define SENS_DAC_CW_EN2_S 25
-/* SENS_DAC_CW_EN1 : R/W; bitpos: [24]; default: 1; */
+/* SENS_DAC_CW_EN1 : RW; bitpos: [24]; default: 1;
+ * 1: to select CW generator as source to PDAC1_DAC[7:0] 0: to select
+ * register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]
+ */
#define SENS_DAC_CW_EN1 (BIT(24))
#define SENS_DAC_CW_EN1_M (SENS_DAC_CW_EN1_V << SENS_DAC_CW_EN1_S)
-#define SENS_DAC_CW_EN1_V 0x1
+#define SENS_DAC_CW_EN1_V 0x00000001
#define SENS_DAC_CW_EN1_S 24
-/* SENS_DAC_INV2 : R/W; bitpos: [23:22]; default: 0; */
+/* SENS_DAC_INV2 : RW; bitpos: [23:22]; default: 0;
+ * 00: do not invert any bits 01: invert all bits 10: invert MSB 11:
+ * invert all bits except MSB
+ */
#define SENS_DAC_INV2 0x00000003
#define SENS_DAC_INV2_M (SENS_DAC_INV2_V << SENS_DAC_INV2_S)
-#define SENS_DAC_INV2_V 0x3
+#define SENS_DAC_INV2_V 0x00000003
#define SENS_DAC_INV2_S 22
-/* SENS_DAC_INV1 : R/W; bitpos: [21:20]; default: 0; */
+/* SENS_DAC_INV1 : RW; bitpos: [21:20]; default: 0;
+ * 00: do not invert any bits 01: invert all bits 10: invert MSB 11:
+ * invert all bits except MSB
+ */
#define SENS_DAC_INV1 0x00000003
#define SENS_DAC_INV1_M (SENS_DAC_INV1_V << SENS_DAC_INV1_S)
-#define SENS_DAC_INV1_V 0x3
+#define SENS_DAC_INV1_V 0x00000003
#define SENS_DAC_INV1_S 20
-/* SENS_DAC_SCALE2 : R/W; bitpos: [19:18]; default: 0; */
+/* SENS_DAC_SCALE2 : RW; bitpos: [19:18]; default: 0;
+ * 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8
+ */
#define SENS_DAC_SCALE2 0x00000003
#define SENS_DAC_SCALE2_M (SENS_DAC_SCALE2_V << SENS_DAC_SCALE2_S)
-#define SENS_DAC_SCALE2_V 0x3
+#define SENS_DAC_SCALE2_V 0x00000003
#define SENS_DAC_SCALE2_S 18
-/* SENS_DAC_SCALE1 : R/W; bitpos: [17:16]; default: 0; */
+/* SENS_DAC_SCALE1 : RW; bitpos: [17:16]; default: 0;
+ * 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8
+ */
#define SENS_DAC_SCALE1 0x00000003
#define SENS_DAC_SCALE1_M (SENS_DAC_SCALE1_V << SENS_DAC_SCALE1_S)
-#define SENS_DAC_SCALE1_V 0x3
+#define SENS_DAC_SCALE1_V 0x00000003
#define SENS_DAC_SCALE1_S 16
-/* SENS_DAC_DC2 : R/W; bitpos: [15:8]; default: 0; */
+/* SENS_DAC_DC2 : RW; bitpos: [15:8]; default: 0;
+ * DC offset for DAC2 CW generator
+ */
#define SENS_DAC_DC2 0x000000ff
#define SENS_DAC_DC2_M (SENS_DAC_DC2_V << SENS_DAC_DC2_S)
-#define SENS_DAC_DC2_V 0xff
+#define SENS_DAC_DC2_V 0x000000ff
#define SENS_DAC_DC2_S 8
-/* SENS_DAC_DC1 : R/W; bitpos: [7:0]; default: 0; */
+/* SENS_DAC_DC1 : RW; bitpos: [7:0]; default: 0;
+ * DC offset for DAC1 CW generator
+ */
#define SENS_DAC_DC1 0x000000ff
#define SENS_DAC_DC1_M (SENS_DAC_DC1_V << SENS_DAC_DC1_S)
-#define SENS_DAC_DC1_V 0xff
+#define SENS_DAC_DC1_V 0x000000ff
#define SENS_DAC_DC1_S 0
+/* SENS_SAR_MEAS_CTRL2_REG register */
+
+#define SENS_SAR_MEAS_CTRL2_REG (DR_REG_SENS_BASE + 0xa0)
+
+/* SENS_AMP_SHORT_REF_GND_FORCE : RW; bitpos: [18:17]; default: 0; */
+
+#define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003
+#define SENS_AMP_SHORT_REF_GND_FORCE_M (SENS_AMP_SHORT_REF_GND_FORCE_V <<
SENS_AMP_SHORT_REF_GND_FORCE_S)
+#define SENS_AMP_SHORT_REF_GND_FORCE_V 0x00000003
+#define SENS_AMP_SHORT_REF_GND_FORCE_S 17
+
+/* SENS_AMP_SHORT_REF_FORCE : RW; bitpos: [16:15]; default: 0; */
+
+#define SENS_AMP_SHORT_REF_FORCE 0x00000003
+#define SENS_AMP_SHORT_REF_FORCE_M (SENS_AMP_SHORT_REF_FORCE_V <<
SENS_AMP_SHORT_REF_FORCE_S)
+#define SENS_AMP_SHORT_REF_FORCE_V 0x00000003
+#define SENS_AMP_SHORT_REF_FORCE_S 15
+
+/* SENS_AMP_RST_FB_FORCE : RW; bitpos: [14:13]; default: 0; */
+
+#define SENS_AMP_RST_FB_FORCE 0x00000003
+#define SENS_AMP_RST_FB_FORCE_M (SENS_AMP_RST_FB_FORCE_V <<
SENS_AMP_RST_FB_FORCE_S)
+#define SENS_AMP_RST_FB_FORCE_V 0x00000003
+#define SENS_AMP_RST_FB_FORCE_S 13
+
+/* SENS_SAR2_RSTB_FORCE : RW; bitpos: [12:11]; default: 0; */
+
+#define SENS_SAR2_RSTB_FORCE 0x00000003
+#define SENS_SAR2_RSTB_FORCE_M (SENS_SAR2_RSTB_FORCE_V <<
SENS_SAR2_RSTB_FORCE_S)
+#define SENS_SAR2_RSTB_FORCE_V 0x00000003
+#define SENS_SAR2_RSTB_FORCE_S 11
+
+/* SENS_SAR_RSTB_FSM_IDLE : RW; bitpos: [10]; default: 0; */
+
+#define SENS_SAR_RSTB_FSM_IDLE (BIT(10))
+#define SENS_SAR_RSTB_FSM_IDLE_M (SENS_SAR_RSTB_FSM_IDLE_V <<
SENS_SAR_RSTB_FSM_IDLE_S)
+#define SENS_SAR_RSTB_FSM_IDLE_V 0x00000001
+#define SENS_SAR_RSTB_FSM_IDLE_S 10
+
+/* SENS_XPD_SAR_FSM_IDLE : RW; bitpos: [9]; default: 0; */
+
+#define SENS_XPD_SAR_FSM_IDLE (BIT(9))
+#define SENS_XPD_SAR_FSM_IDLE_M (SENS_XPD_SAR_FSM_IDLE_V <<
SENS_XPD_SAR_FSM_IDLE_S)
+#define SENS_XPD_SAR_FSM_IDLE_V 0x00000001
+#define SENS_XPD_SAR_FSM_IDLE_S 9
+
+/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : RW; bitpos: [8]; default: 0; */
+
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(8))
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (SENS_AMP_SHORT_REF_GND_FSM_IDLE_V
<< SENS_AMP_SHORT_REF_GND_FSM_IDLE_S)
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x00000001
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 8
+
+/* SENS_AMP_SHORT_REF_FSM_IDLE : RW; bitpos: [7]; default: 0; */
+
+#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(7))
+#define SENS_AMP_SHORT_REF_FSM_IDLE_M (SENS_AMP_SHORT_REF_FSM_IDLE_V <<
SENS_AMP_SHORT_REF_FSM_IDLE_S)
+#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x00000001
+#define SENS_AMP_SHORT_REF_FSM_IDLE_S 7
+
+/* SENS_AMP_RST_FB_FSM_IDLE : RW; bitpos: [6]; default: 0; */
+
+#define SENS_AMP_RST_FB_FSM_IDLE (BIT(6))
+#define SENS_AMP_RST_FB_FSM_IDLE_M (SENS_AMP_RST_FB_FSM_IDLE_V <<
SENS_AMP_RST_FB_FSM_IDLE_S)
+#define SENS_AMP_RST_FB_FSM_IDLE_V 0x00000001
+#define SENS_AMP_RST_FB_FSM_IDLE_S 6
+
+/* SENS_XPD_SAR_AMP_FSM_IDLE : RW; bitpos: [5]; default: 0; */
+
+#define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(5))
+#define SENS_XPD_SAR_AMP_FSM_IDLE_M (SENS_XPD_SAR_AMP_FSM_IDLE_V <<
SENS_XPD_SAR_AMP_FSM_IDLE_S)
+#define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x00000001
+#define SENS_XPD_SAR_AMP_FSM_IDLE_S 5
+
+/* SENS_SAR1_DAC_XPD_FSM_IDLE : RW; bitpos: [4]; default: 0; */
+
+#define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(4))
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_M (SENS_SAR1_DAC_XPD_FSM_IDLE_V <<
SENS_SAR1_DAC_XPD_FSM_IDLE_S)
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x00000001
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_S 4
+
+/* SENS_SAR1_DAC_XPD_FSM : RW; bitpos: [3:0]; default: 3; */
+
+#define SENS_SAR1_DAC_XPD_FSM 0x0000000f
+#define SENS_SAR1_DAC_XPD_FSM_M (SENS_SAR1_DAC_XPD_FSM_V <<
SENS_SAR1_DAC_XPD_FSM_S)
+#define SENS_SAR1_DAC_XPD_FSM_V 0x0000000f
+#define SENS_SAR1_DAC_XPD_FSM_S 0
+
+/* SENS_SAR_NOUSE_REG register */
+
+#define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0xf8)
+
+/* SENS_SAR_NOUSE : RW; bitpos: [31:0]; default: 0; */
+
+#define SENS_SAR_NOUSE 0xffffffff
+#define SENS_SAR_NOUSE_M (SENS_SAR_NOUSE_V << SENS_SAR_NOUSE_S)
+#define SENS_SAR_NOUSE_V 0xffffffff
+#define SENS_SAR_NOUSE_S 0
+
+/* SENS_SARDATE_REG register */
+
+#define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0xfc)
+
+/* SENS_SAR_DATE : RW; bitpos: [27:0]; default: 23089536; */
+
+#define SENS_SAR_DATE 0x0fffffff
+#define SENS_SAR_DATE_M (SENS_SAR_DATE_V << SENS_SAR_DATE_S)
+#define SENS_SAR_DATE_V 0x0fffffff
+#define SENS_SAR_DATE_S 0
+
#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SENS_H */
diff --git a/boards/xtensa/esp32/common/include/esp32_board_dac.h
b/boards/xtensa/esp32/common/include/esp32_board_dac.h
new file mode 100644
index 0000000000..b364590db7
--- /dev/null
+++ b/boards/xtensa/esp32/common/include/esp32_board_dac.h
@@ -0,0 +1,84 @@
+/****************************************************************************
+ * boards/xtensa/esp32/common/include/esp32_board_dac.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_ESP32_DAC_H
+#define __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_ESP32_DAC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_dac_initialize
+ *
+ * Description:
+ * Initialize and register the Digital to Analog Convertor (DAC) driver.
+ *
+ * Input Parameters:
+ * path - The device number, used to build the device path as
+ * /dev/dacN
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int board_dac_initialize(const char *path);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_ESP32_DAC_H */
diff --git a/boards/xtensa/esp32/common/src/Make.defs
b/boards/xtensa/esp32/common/src/Make.defs
index 121dea0e4f..41ff806de8 100644
--- a/boards/xtensa/esp32/common/src/Make.defs
+++ b/boards/xtensa/esp32/common/src/Make.defs
@@ -144,6 +144,10 @@ ifeq ($(CONFIG_ESP32_RMT),y)
CSRCS += esp32_rmt.c
endif
+#ifeq ($(CONFIG_DAC),y)
+ CSRCS += esp32_board_dac.c
+#endif
+
DEPPATH += --dep-path src
VPATH += :src
CFLAGS +=
${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src
diff --git a/boards/xtensa/esp32/common/src/esp32_board_dac.c
b/boards/xtensa/esp32/common/src/esp32_board_dac.c
new file mode 100644
index 0000000000..fb71f35b12
--- /dev/null
+++ b/boards/xtensa/esp32/common/src/esp32_board_dac.c
@@ -0,0 +1,79 @@
+/****************************************************************************
+ * boards/xtensa/esp32/common/src/esp32_board_dac.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/analog/dac.h>
+#include <stdio.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <esp32_dac.h>
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_dac_initialize
+ *
+ * Description:
+ * Initialize and register the Digital to Analog Convertor (DAC) driver.
+ *
+ * Input Parameters:
+ * path - The device number, used to build the device path as
+ * /dev/dacN
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int board_dac_initialize(const char *path)
+{
+ int ret;
+
+ /* Initialize DAC */
+
+ struct dac_dev_s *dev = esp32_dac_initialize();
+ if (dev != NULL)
+ {
+ /* Try to register the DAC */
+
+ ret = dac_register(path, dev);
+ if (ret < 0)
+ {
+ snerr("ERROR: Error registering DAC\n");
+ }
+ }
+ else
+ {
+ ret = -ENODEV;
+ }
+
+ return ret;
+}
diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/dac/defconfig
b/boards/xtensa/esp32/esp32-devkitc/configs/dac/defconfig
new file mode 100644
index 0000000000..b6d18afecb
--- /dev/null
+++ b/boards/xtensa/esp32/esp32-devkitc/configs/dac/defconfig
@@ -0,0 +1,48 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed
.config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that
includes your
+# modifications.
+#
+# CONFIG_ARCH_LEDS is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_ANALOG=y
+CONFIG_ARCH="xtensa"
+CONFIG_ARCH_BOARD="esp32-devkitc"
+CONFIG_ARCH_BOARD_COMMON=y
+CONFIG_ARCH_BOARD_ESP32_DEVKITC=y
+CONFIG_ARCH_CHIP="esp32"
+CONFIG_ARCH_CHIP_ESP32=y
+CONFIG_ARCH_CHIP_ESP32WROVER=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_XTENSA=y
+CONFIG_BOARD_LOOPSPERMSEC=16717
+CONFIG_BUILTIN=y
+CONFIG_DAC=y
+CONFIG_ESP32_UART0=y
+CONFIG_EXAMPLES_DAC=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_IDLETHREAD_STACKSIZE=3072
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MM_REGIONS=3
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=114688
+CONFIG_RAM_START=0x20000000
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_SYSLOG_BUFFER=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_UART0_SERIAL_CONSOLE=y
diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c
b/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c
index dd384b163e..9986baa90f 100644
--- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c
+++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c
@@ -165,6 +165,10 @@
# include "esp32_rmt.h"
#endif
+#ifdef CONFIG_DAC
+# include "esp32_board_dac.h"
+#endif
+
#include "esp32-devkitc.h"
/****************************************************************************
@@ -645,6 +649,14 @@ int esp32_bringup(void)
}
#endif
+#ifdef CONFIG_DAC
+ ret = board_dac_initialize(CONFIG_ESP32_DAC_DEVPATH);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: board_dac_initialize(0) failed: %d\n", ret);
+ }
+#endif
+
#ifdef CONFIG_RTC_DRIVER
/* Instantiate the ESP32 RTC driver */
