hartmannathan commented on a change in pull request #1051: URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426288585
########## File path: arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h ########## @@ -0,0 +1,194 @@ +/**************************************************************************************************** + * arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* STM32G47xxx Address Blocks ***********************************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ +#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM */ + /* 0x70000000-0x7fffffff: Reserved */ +#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +#define STM32_QSPI_BANK1 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ + +#define STM32_FMC_QSPI_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 256Mb FMC and QUADSPI registers */ + /* 0xc0000000-0xdfffffff: Reserved */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK Warning Not Cleared! 0xf0000000 +#define STM32_IS_SRAM(a) Warning Not Cleared! ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) + +/* Code Base Addresses ******************************************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x0007ffff: Aliased boot memory */ + /* 0x00080000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x807ffff: Up to 512Kb FLASH memory */ + /* 0x08080000-0xfffffff: Reserved */ +#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x10007fff: 32Kb CCM data SRAM */ + /* 0x10008000-0x1ffeffff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: 28Kb System memory */ +#define STM32_OTP_AREA_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: 1Kb OTP area */ + /* 0x1fff7400-0x1fff77ff: Reserved */ +#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: 16 Option bytes */ + /* 0x1fff7810-0x1fff7fff: Reserved */ +#define STM32_SYSMEM_BASE2 0x1fff8000 /* 0x1fff8000-0x1fffefff: 28Kb System memory */ + /* 0x1ffff000-0x1ffff7ff: Reserved */ +#define STM32_OPTION_BASE2 0x1ffff800 /* 0x1ffff800-0x1ffff80f: 16 Option bytes */ + /* 0x1fff7810-0x1fff7fff: Reserved */ + +/* System Memory Addresses **************************************************************************/ + +#define STM32_PACKAGE_INFO 0x1fff7500 /* Package data register */ +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of + * the device Flash memory expressed in + * Kbytes. Example: 0x040 corresponds + * to 64 Kbytes + */ + +/* Peripheral Base Addresses ************************************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ + /* 0x40009800-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */ + /* 0x40016400-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x47ffffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */ + /* 0x50060c00-0x5fffffff: Reserved */ + +/* APB1 Base Addresses ******************************************************************************/ + Review comment: Fixed in c293babe6827d9f9c45dd2781fdeb1d167d1a814. ---------------------------------------------------------------- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. 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