raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426270135
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File path: arch/arm/src/stm32/hardware/stm32_adc_v2.h
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@@ -86,18 +86,24 @@
/* Base addresses
***********************************************************************************/
-#define STM32_ADC1_OFFSET 0x0000
-#define STM32_ADC2_OFFSET 0x0100
-#define STM32_ADC3_OFFSET 0x0000
-#define STM32_ADC4_OFFSET 0x0100
-#define STM32_ADCCMN_OFFSET 0x0300
+/* G47x has the ADC base addresses are defined in stm32g47xxx_memorymap.h.
+ * Other P/Ns have ADC base addresses are defined here.
+ */
-#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /*
ADC1 Master ADC */
-#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /*
ADC2 Slave ADC */
-#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /*
ADC3 Master ADC */
-#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /*
ADC4 Slave ADC */
-#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE)
/* ADC1, ADC2 common */
-#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE)
/* ADC3, ADC4 common */
+#if !defined(CONFIG_STM32_STM32G47XX)
Review comment:
If you look at the memory map in reference manual, you'll see that the
ADCs are grouped into blocks. We have only two independent ADC blocks: ADC12
and ADC345. This means that ADC1 and ADC2 (or ADC3, ADC4 and ADC5) are not
separate units that can be controlled independently, but they are closely
related. So basically there is no peripherals such as ADC1 or ADC2, but it is
ADC12 and this should be reflected in the memory map.
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