https://github.com/XChy updated https://github.com/llvm/llvm-project/pull/234629
>From 548fbc41a75bf558fd46f4e443978719c45ecece Mon Sep 17 00:00:00 2001 From: XChy <[email protected]> Date: Fri, 16 Oct 2026 17:26:48 +0800 Subject: [PATCH 1/3] [RISCV][P-ext] Support Packed Slide --- clang/lib/Headers/riscv_packed_simd.h | 44 ++ clang/test/CodeGen/RISCV/rvp-intrinsics.c | 391 ++++++++++++++++++ .../riscv_packed_simd.c | 132 ++++++ llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 90 ++++ llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 204 +++++++++ 5 files changed, 861 insertions(+) diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index c91cf66d0b31af..37cbecf286e1f4 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -179,6 +179,24 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8))); return __builtin_elementwise_fshr(__rs1, __rd, (ty)__shamt); \ } +#define __packed_slideupx(name, ty, bits_ty, log2_elt_bits) \ + static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \ + unsigned __rs2) { \ + bits_ty __bits = __builtin_elementwise_fshl( \ + __builtin_bit_cast(bits_ty, __rd), __builtin_bit_cast(bits_ty, __rs1), \ + (bits_ty)__rs2 << (log2_elt_bits)); \ + return __builtin_bit_cast(ty, __bits); \ + } + +#define __packed_slidedownx(name, ty, bits_ty, log2_elt_bits) \ + static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \ + unsigned __rs2) { \ + bits_ty __bits = __builtin_elementwise_fshr( \ + __builtin_bit_cast(bits_ty, __rs1), __builtin_bit_cast(bits_ty, __rd), \ + (bits_ty)__rs2 << (log2_elt_bits)); \ + return __builtin_bit_cast(ty, __bits); \ + } + #define __packed_widen_convert(name, rty, ty) \ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \ return __builtin_convertvector(__rs1, rty); \ @@ -1446,6 +1464,30 @@ __packed_slide1(pslide1down_u16x4, uint16x4_t, uint16_t, 1, 2, 3, 4) __packed_slide1(pslide1down_i32x2, int32x2_t, int32_t, 1, 2) __packed_slide1(pslide1down_u32x2, uint32x2_t, uint32_t, 1, 2) +/* Packed Slide (32-bit) */ +__packed_slideupx(pslideupx_i8x4, int8x4_t, uint32_t, 3) +__packed_slideupx(pslideupx_u8x4, uint8x4_t, uint32_t, 3) +__packed_slideupx(pslideupx_i16x2, int16x2_t, uint32_t, 4) +__packed_slideupx(pslideupx_u16x2, uint16x2_t, uint32_t, 4) +__packed_slidedownx(pslidedownx_i8x4, int8x4_t, uint32_t, 3) +__packed_slidedownx(pslidedownx_u8x4, uint8x4_t, uint32_t, 3) +__packed_slidedownx(pslidedownx_i16x2, int16x2_t, uint32_t, 4) +__packed_slidedownx(pslidedownx_u16x2, uint16x2_t, uint32_t, 4) + +/* Packed Slide (64-bit) */ +__packed_slideupx(pslideupx_i8x8, int8x8_t, uint64_t, 3) +__packed_slideupx(pslideupx_u8x8, uint8x8_t, uint64_t, 3) +__packed_slideupx(pslideupx_i16x4, int16x4_t, uint64_t, 4) +__packed_slideupx(pslideupx_u16x4, uint16x4_t, uint64_t, 4) +__packed_slideupx(pslideupx_i32x2, int32x2_t, uint64_t, 5) +__packed_slideupx(pslideupx_u32x2, uint32x2_t, uint64_t, 5) +__packed_slidedownx(pslidedownx_i8x8, int8x8_t, uint64_t, 3) +__packed_slidedownx(pslidedownx_u8x8, uint8x8_t, uint64_t, 3) +__packed_slidedownx(pslidedownx_i16x4, int16x4_t, uint64_t, 4) +__packed_slidedownx(pslidedownx_u16x4, uint16x4_t, uint64_t, 4) +__packed_slidedownx(pslidedownx_i32x2, int32x2_t, uint64_t, 5) +__packed_slidedownx(pslidedownx_u32x2, uint32x2_t, uint64_t, 5) + /* Packed Subvector Extract */ __packed_subvector_extract8(pget_i8x8_i8x4, int8x4_t, int8x8_t) __packed_subvector_extract8(pget_u8x8_u8x4, uint8x4_t, uint8x8_t) @@ -1647,6 +1689,8 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t) #undef __packed_cls #undef __packed_slx #undef __packed_srx +#undef __packed_slideupx +#undef __packed_slidedownx #undef __packed_widen_convert #undef __packed_widen_binary_op #undef __packed_widen_binary_acc_op diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 2233e5835ea1e7..ef479a04af5dc2 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -10224,3 +10224,394 @@ int64_t test_pm2wsuba_x_i64(int64_t rd, int16x2_t rs1, int16x2_t rs2) { int64_t test_pm2waddasu_i64(int64_t rd, int16x2_t rs1, uint16x2_t rs2) { return __riscv_pm2waddasu_i64(rd, rs1, rs2); } + +/* Packed Slide (32-bit) */ + +// RV32-LABEL: define dso_local i32 @test_pslideupx_i8x4( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslideupx_i8x4( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +int8x4_t test_pslideupx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_i8x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslideupx_u8x4( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslideupx_u8x4( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +uint8x4_t test_pslideupx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_u8x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslideupx_i16x2( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslideupx_i16x2( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +int16x2_t test_pslideupx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_i16x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslideupx_u16x2( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslideupx_u16x2( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +uint16x2_t test_pslideupx_u16x2(uint16x2_t rd, uint16x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_u16x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslidedownx_i8x4( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslidedownx_i8x4( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +int8x4_t test_pslidedownx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i8x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslidedownx_u8x4( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslidedownx_u8x4( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +uint8x4_t test_pslidedownx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) { + return __riscv_pslidedownx_u8x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslidedownx_i16x2( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslidedownx_i16x2( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +int16x2_t test_pslidedownx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i16x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslidedownx_u16x2( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslidedownx_u16x2( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +uint16x2_t test_pslidedownx_u16x2(uint16x2_t rd, uint16x2_t rs1, + unsigned rs2) { + return __riscv_pslidedownx_u16x2(rd, rs1, rs2); +} + +/* Packed Slide (64-bit) */ + +// RV32-LABEL: define dso_local i64 @test_pslideupx_i8x8( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_i8x8( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +int8x8_t test_pslideupx_i8x8(int8x8_t rd, int8x8_t rs1, unsigned rs2) { + return __riscv_pslideupx_i8x8(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslideupx_u8x8( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_u8x8( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +uint8x8_t test_pslideupx_u8x8(uint8x8_t rd, uint8x8_t rs1, unsigned rs2) { + return __riscv_pslideupx_u8x8(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslideupx_i16x4( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_i16x4( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +int16x4_t test_pslideupx_i16x4(int16x4_t rd, int16x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_i16x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslideupx_u16x4( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_u16x4( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +uint16x4_t test_pslideupx_u16x4(uint16x4_t rd, uint16x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_u16x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslideupx_i32x2( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_i32x2( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +int32x2_t test_pslideupx_i32x2(int32x2_t rd, int32x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_i32x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslideupx_u32x2( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_u32x2( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +uint32x2_t test_pslideupx_u32x2(uint32x2_t rd, uint32x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_u32x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslidedownx_i8x8( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslidedownx_i8x8( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +int8x8_t test_pslidedownx_i8x8(int8x8_t rd, int8x8_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i8x8(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslidedownx_u8x8( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslidedownx_u8x8( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +uint8x8_t test_pslidedownx_u8x8(uint8x8_t rd, uint8x8_t rs1, unsigned rs2) { + return __riscv_pslidedownx_u8x8(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslidedownx_i16x4( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslidedownx_i16x4( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +int16x4_t test_pslidedownx_i16x4(int16x4_t rd, int16x4_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i16x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslidedownx_u16x4( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslidedownx_u16x4( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +uint16x4_t test_pslidedownx_u16x4(uint16x4_t rd, uint16x4_t rs1, + unsigned rs2) { + return __riscv_pslidedownx_u16x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslidedownx_i32x2( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslidedownx_i32x2( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +int32x2_t test_pslidedownx_i32x2(int32x2_t rd, int32x2_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i32x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslidedownx_u32x2( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslidedownx_u32x2( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +uint32x2_t test_pslidedownx_u32x2(uint32x2_t rd, uint32x2_t rs1, + unsigned rs2) { + return __riscv_pslidedownx_u32x2(rd, rs1, rs2); +} diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 526ba7bd3c630f..35474265ef3e60 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -6063,3 +6063,135 @@ int32x2_t test_pslide1down_i32x2(int32x2_t rd, int32_t rs1) { uint32x2_t test_pslide1down_u32x2(uint32x2_t rd, uint32_t rs1) { return __riscv_pslide1down_u32x2(rd, rs1); } + +/* Packed Slide (32-bit) */ + +// CHECK-LABEL: test_pslideupx_i8x4: +// CHECK: slx +int8x4_t test_pslideupx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_i8x4(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslideupx_u8x4: +// CHECK: slx +uint8x4_t test_pslideupx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_u8x4(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslideupx_i16x2: +// CHECK: slx +int16x2_t test_pslideupx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_i16x2(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslideupx_u16x2: +// CHECK: slx +uint16x2_t test_pslideupx_u16x2(uint16x2_t rd, uint16x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_u16x2(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslidedownx_i8x4: +// RV32: srx +// RV64: pack +// RV64: srl +int8x4_t test_pslidedownx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i8x4(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslidedownx_u8x4: +// RV32: srx +// RV64: pack +// RV64: srl +uint8x4_t test_pslidedownx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) { + return __riscv_pslidedownx_u8x4(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslidedownx_i16x2: +// RV32: srx +// RV64: pack +// RV64: srl +int16x2_t test_pslidedownx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i16x2(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslidedownx_u16x2: +// RV32: srx +// RV64: pack +// RV64: srl +uint16x2_t test_pslidedownx_u16x2(uint16x2_t rd, uint16x2_t rs1, unsigned rs2) { + return __riscv_pslidedownx_u16x2(rd, rs1, rs2); +} + +/* Packed Slide (64-bit) */ + +// CHECK-LABEL: test_pslideupx_i8x8: +// CHECK: slx +int8x8_t test_pslideupx_i8x8(int8x8_t rd, int8x8_t rs1, unsigned rs2) { + return __riscv_pslideupx_i8x8(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslideupx_u8x8: +// CHECK: slx +uint8x8_t test_pslideupx_u8x8(uint8x8_t rd, uint8x8_t rs1, unsigned rs2) { + return __riscv_pslideupx_u8x8(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslideupx_i16x4: +// CHECK: slx +int16x4_t test_pslideupx_i16x4(int16x4_t rd, int16x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_i16x4(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslideupx_u16x4: +// CHECK: slx +uint16x4_t test_pslideupx_u16x4(uint16x4_t rd, uint16x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_u16x4(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslideupx_i32x2: +// RV64: slx +int32x2_t test_pslideupx_i32x2(int32x2_t rd, int32x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_i32x2(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslideupx_u32x2: +// RV64: slx +uint32x2_t test_pslideupx_u32x2(uint32x2_t rd, uint32x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_u32x2(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslidedownx_i8x8: +// CHECK: srx +int8x8_t test_pslidedownx_i8x8(int8x8_t rd, int8x8_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i8x8(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslidedownx_u8x8: +// CHECK: srx +uint8x8_t test_pslidedownx_u8x8(uint8x8_t rd, uint8x8_t rs1, unsigned rs2) { + return __riscv_pslidedownx_u8x8(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslidedownx_i16x4: +// CHECK: srx +int16x4_t test_pslidedownx_i16x4(int16x4_t rd, int16x4_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i16x4(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslidedownx_u16x4: +// CHECK: srx +uint16x4_t test_pslidedownx_u16x4(uint16x4_t rd, uint16x4_t rs1, unsigned rs2) { + return __riscv_pslidedownx_u16x4(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslidedownx_i32x2: +// RV64: srx +int32x2_t test_pslidedownx_i32x2(int32x2_t rd, int32x2_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i32x2(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pslidedownx_u32x2: +// RV64: srx +uint32x2_t test_pslidedownx_u32x2(uint32x2_t rd, uint32x2_t rs1, unsigned rs2) { + return __riscv_pslidedownx_u32x2(rd, rs1, rs2); +} diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll index 4c9279872cdcff..202d0959b424a9 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll @@ -4150,3 +4150,93 @@ define <2 x i16> @test_pslide1down_v2i16(<2 x i16> %rd, i16 %rs1) { %res = shufflevector <2 x i16> %rd, <2 x i16> %scalar, <2 x i32> <i32 1, i32 2> ret <2 x i16> %res } + +define <4 x i8> @test_pslideupx_v4i8(<4 x i8> %rd, <4 x i8> %rs1, i32 %rs2) { +; RV32-LABEL: test_pslideupx_v4i8: +; RV32: # %bb.0: +; RV32-NEXT: slli a2, a2, 3 +; RV32-NEXT: slx a0, a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pslideupx_v4i8: +; RV64: # %bb.0: +; RV64-NEXT: slli a2, a2, 3 +; RV64-NEXT: slli a1, a1, 32 +; RV64-NEXT: andi a2, a2, 24 +; RV64-NEXT: slx a0, a1, a2 +; RV64-NEXT: ret + %rd.bits = bitcast <4 x i8> %rd to i32 + %rs1.bits = bitcast <4 x i8> %rs1 to i32 + %shamt = shl i32 %rs2, 3 + %res.bits = call i32 @llvm.fshl.i32(i32 %rd.bits, i32 %rs1.bits, i32 %shamt) + %res = bitcast i32 %res.bits to <4 x i8> + ret <4 x i8> %res +} + +define <4 x i8> @test_pslidedownx_v4i8(<4 x i8> %rd, <4 x i8> %rs1, i32 %rs2) { +; RV32-LABEL: test_pslidedownx_v4i8: +; RV32: # %bb.0: +; RV32-NEXT: slli a2, a2, 3 +; RV32-NEXT: srx a0, a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pslidedownx_v4i8: +; RV64: # %bb.0: +; RV64-NEXT: slli a2, a2, 3 +; RV64-NEXT: slli a0, a0, 32 +; RV64-NEXT: ori a2, a2, 32 +; RV64-NEXT: srx a0, a1, a2 +; RV64-NEXT: ret + %rd.bits = bitcast <4 x i8> %rd to i32 + %rs1.bits = bitcast <4 x i8> %rs1 to i32 + %shamt = shl i32 %rs2, 3 + %res.bits = call i32 @llvm.fshr.i32(i32 %rs1.bits, i32 %rd.bits, i32 %shamt) + %res = bitcast i32 %res.bits to <4 x i8> + ret <4 x i8> %res +} + +define <2 x i16> @test_pslideupx_v2i16(<2 x i16> %rd, <2 x i16> %rs1, + i32 %rs2) { +; RV32-LABEL: test_pslideupx_v2i16: +; RV32: # %bb.0: +; RV32-NEXT: slli a2, a2, 4 +; RV32-NEXT: slx a0, a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pslideupx_v2i16: +; RV64: # %bb.0: +; RV64-NEXT: slli a2, a2, 4 +; RV64-NEXT: slli a1, a1, 32 +; RV64-NEXT: andi a2, a2, 16 +; RV64-NEXT: slx a0, a1, a2 +; RV64-NEXT: ret + %rd.bits = bitcast <2 x i16> %rd to i32 + %rs1.bits = bitcast <2 x i16> %rs1 to i32 + %shamt = shl i32 %rs2, 4 + %res.bits = call i32 @llvm.fshl.i32(i32 %rd.bits, i32 %rs1.bits, i32 %shamt) + %res = bitcast i32 %res.bits to <2 x i16> + ret <2 x i16> %res +} + +define <2 x i16> @test_pslidedownx_v2i16(<2 x i16> %rd, <2 x i16> %rs1, + i32 %rs2) { +; RV32-LABEL: test_pslidedownx_v2i16: +; RV32: # %bb.0: +; RV32-NEXT: slli a2, a2, 4 +; RV32-NEXT: srx a0, a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pslidedownx_v2i16: +; RV64: # %bb.0: +; RV64-NEXT: slli a2, a2, 4 +; RV64-NEXT: slli a0, a0, 32 +; RV64-NEXT: ori a2, a2, 32 +; RV64-NEXT: srx a0, a1, a2 +; RV64-NEXT: ret + %rd.bits = bitcast <2 x i16> %rd to i32 + %rs1.bits = bitcast <2 x i16> %rs1 to i32 + %shamt = shl i32 %rs2, 4 + %res.bits = call i32 @llvm.fshr.i32(i32 %rs1.bits, i32 %rd.bits, i32 %shamt) + %res = bitcast i32 %res.bits to <2 x i16> + ret <2 x i16> %res +} diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll index e79a69131e7b89..8d26dffca25474 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll @@ -9037,3 +9037,207 @@ define <2 x i32> @test_pslide1down_v2i32(<2 x i32> %rd, i32 %rs1) { %res = shufflevector <2 x i32> %rd, <2 x i32> %scalar, <2 x i32> <i32 1, i32 2> ret <2 x i32> %res } + +define <8 x i8> @test_pslideupx_v8i8(<8 x i8> %rd, <8 x i8> %rs1, i32 %rs2) { +; RV32-LABEL: test_pslideupx_v8i8: +; RV32: # %bb.0: +; RV32-NEXT: mv a5, a0 +; RV32-NEXT: slli a0, a4, 29 +; RV32-NEXT: srli a6, a0, 31 +; RV32-NEXT: slli a4, a4, 3 +; RV32-NEXT: bnez a6, .LBB513_2 +; RV32-NEXT: # %bb.1: +; RV32-NEXT: mv a0, a5 +; RV32-NEXT: mv a5, a1 +; RV32-NEXT: slx a5, a0, a4 +; RV32-NEXT: beqz a6, .LBB513_3 +; RV32-NEXT: j .LBB513_4 +; RV32-NEXT: .LBB513_2: +; RV32-NEXT: mv a0, a3 +; RV32-NEXT: slx a5, a3, a4 +; RV32-NEXT: bnez a6, .LBB513_4 +; RV32-NEXT: .LBB513_3: +; RV32-NEXT: mv a2, a3 +; RV32-NEXT: .LBB513_4: +; RV32-NEXT: slx a0, a2, a4 +; RV32-NEXT: mv a1, a5 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pslideupx_v8i8: +; RV64: # %bb.0: +; RV64-NEXT: slli a2, a2, 3 +; RV64-NEXT: slx a0, a1, a2 +; RV64-NEXT: ret + %rd.bits = bitcast <8 x i8> %rd to i64 + %rs1.bits = bitcast <8 x i8> %rs1 to i64 + %rs2.ext = zext i32 %rs2 to i64 + %shamt = shl i64 %rs2.ext, 3 + %res.bits = call i64 @llvm.fshl.i64(i64 %rd.bits, i64 %rs1.bits, i64 %shamt) + %res = bitcast i64 %res.bits to <8 x i8> + ret <8 x i8> %res +} + +define <8 x i8> @test_pslidedownx_v8i8(<8 x i8> %rd, <8 x i8> %rs1, + i32 %rs2) { +; RV32-LABEL: test_pslidedownx_v8i8: +; RV32: # %bb.0: +; RV32-NEXT: slli a5, a4, 3 +; RV32-NEXT: andi a6, a5, 32 +; RV32-NEXT: bnez a6, .LBB514_2 +; RV32-NEXT: # %bb.1: +; RV32-NEXT: mv a3, a2 +; RV32-NEXT: mv a2, a1 +; RV32-NEXT: .LBB514_2: +; RV32-NEXT: mv a4, a2 +; RV32-NEXT: srx a4, a3, a5 +; RV32-NEXT: beqz a6, .LBB514_4 +; RV32-NEXT: # %bb.3: +; RV32-NEXT: mv a0, a1 +; RV32-NEXT: .LBB514_4: +; RV32-NEXT: srx a0, a2, a5 +; RV32-NEXT: mv a1, a4 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pslidedownx_v8i8: +; RV64: # %bb.0: +; RV64-NEXT: slli a2, a2, 3 +; RV64-NEXT: srx a0, a1, a2 +; RV64-NEXT: ret + %rd.bits = bitcast <8 x i8> %rd to i64 + %rs1.bits = bitcast <8 x i8> %rs1 to i64 + %rs2.ext = zext i32 %rs2 to i64 + %shamt = shl i64 %rs2.ext, 3 + %res.bits = call i64 @llvm.fshr.i64(i64 %rs1.bits, i64 %rd.bits, i64 %shamt) + %res = bitcast i64 %res.bits to <8 x i8> + ret <8 x i8> %res +} + +define <4 x i16> @test_pslideupx_v4i16(<4 x i16> %rd, <4 x i16> %rs1, + i32 %rs2) { +; RV32-LABEL: test_pslideupx_v4i16: +; RV32: # %bb.0: +; RV32-NEXT: mv a5, a0 +; RV32-NEXT: slli a0, a4, 30 +; RV32-NEXT: srli a6, a0, 31 +; RV32-NEXT: slli a4, a4, 4 +; RV32-NEXT: bnez a6, .LBB515_2 +; RV32-NEXT: # %bb.1: +; RV32-NEXT: mv a0, a5 +; RV32-NEXT: mv a5, a1 +; RV32-NEXT: slx a5, a0, a4 +; RV32-NEXT: beqz a6, .LBB515_3 +; RV32-NEXT: j .LBB515_4 +; RV32-NEXT: .LBB515_2: +; RV32-NEXT: mv a0, a3 +; RV32-NEXT: slx a5, a3, a4 +; RV32-NEXT: bnez a6, .LBB515_4 +; RV32-NEXT: .LBB515_3: +; RV32-NEXT: mv a2, a3 +; RV32-NEXT: .LBB515_4: +; RV32-NEXT: slx a0, a2, a4 +; RV32-NEXT: mv a1, a5 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pslideupx_v4i16: +; RV64: # %bb.0: +; RV64-NEXT: slli a2, a2, 4 +; RV64-NEXT: slx a0, a1, a2 +; RV64-NEXT: ret + %rd.bits = bitcast <4 x i16> %rd to i64 + %rs1.bits = bitcast <4 x i16> %rs1 to i64 + %rs2.ext = zext i32 %rs2 to i64 + %shamt = shl i64 %rs2.ext, 4 + %res.bits = call i64 @llvm.fshl.i64(i64 %rd.bits, i64 %rs1.bits, i64 %shamt) + %res = bitcast i64 %res.bits to <4 x i16> + ret <4 x i16> %res +} + +define <4 x i16> @test_pslidedownx_v4i16(<4 x i16> %rd, <4 x i16> %rs1, + i32 %rs2) { +; RV32-LABEL: test_pslidedownx_v4i16: +; RV32: # %bb.0: +; RV32-NEXT: slli a5, a4, 4 +; RV32-NEXT: andi a6, a5, 32 +; RV32-NEXT: bnez a6, .LBB516_2 +; RV32-NEXT: # %bb.1: +; RV32-NEXT: mv a3, a2 +; RV32-NEXT: mv a2, a1 +; RV32-NEXT: .LBB516_2: +; RV32-NEXT: mv a4, a2 +; RV32-NEXT: srx a4, a3, a5 +; RV32-NEXT: beqz a6, .LBB516_4 +; RV32-NEXT: # %bb.3: +; RV32-NEXT: mv a0, a1 +; RV32-NEXT: .LBB516_4: +; RV32-NEXT: srx a0, a2, a5 +; RV32-NEXT: mv a1, a4 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pslidedownx_v4i16: +; RV64: # %bb.0: +; RV64-NEXT: slli a2, a2, 4 +; RV64-NEXT: srx a0, a1, a2 +; RV64-NEXT: ret + %rd.bits = bitcast <4 x i16> %rd to i64 + %rs1.bits = bitcast <4 x i16> %rs1 to i64 + %rs2.ext = zext i32 %rs2 to i64 + %shamt = shl i64 %rs2.ext, 4 + %res.bits = call i64 @llvm.fshr.i64(i64 %rs1.bits, i64 %rd.bits, i64 %shamt) + %res = bitcast i64 %res.bits to <4 x i16> + ret <4 x i16> %res +} + +define <2 x i32> @test_pslideupx_v2i32(<2 x i32> %rd, <2 x i32> %rs1, + i32 %rs2) { +; RV32-LABEL: test_pslideupx_v2i32: +; RV32: # %bb.0: +; RV32-NEXT: andi a4, a4, 1 +; RV32-NEXT: beqz a4, .LBB517_2 +; RV32-NEXT: # %bb.1: +; RV32-NEXT: mv a1, a0 +; RV32-NEXT: mv a0, a3 +; RV32-NEXT: .LBB517_2: +; RV32-NEXT: ret +; +; RV64-LABEL: test_pslideupx_v2i32: +; RV64: # %bb.0: +; RV64-NEXT: slli a2, a2, 5 +; RV64-NEXT: slx a0, a1, a2 +; RV64-NEXT: ret + %rd.bits = bitcast <2 x i32> %rd to i64 + %rs1.bits = bitcast <2 x i32> %rs1 to i64 + %rs2.ext = zext i32 %rs2 to i64 + %shamt = shl i64 %rs2.ext, 5 + %res.bits = call i64 @llvm.fshl.i64(i64 %rd.bits, i64 %rs1.bits, i64 %shamt) + %res = bitcast i64 %res.bits to <2 x i32> + ret <2 x i32> %res +} + +define <2 x i32> @test_pslidedownx_v2i32(<2 x i32> %rd, <2 x i32> %rs1, + i32 %rs2) { +; RV32-LABEL: test_pslidedownx_v2i32: +; RV32: # %bb.0: +; RV32-NEXT: slli a4, a4, 31 +; RV32-NEXT: srli a4, a4, 26 +; RV32-NEXT: bnez a4, .LBB518_2 +; RV32-NEXT: # %bb.1: +; RV32-NEXT: mv a2, a1 +; RV32-NEXT: mv a1, a0 +; RV32-NEXT: .LBB518_2: +; RV32-NEXT: mv a0, a1 +; RV32-NEXT: mv a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pslidedownx_v2i32: +; RV64: # %bb.0: +; RV64-NEXT: slli a2, a2, 5 +; RV64-NEXT: srx a0, a1, a2 +; RV64-NEXT: ret + %rd.bits = bitcast <2 x i32> %rd to i64 + %rs1.bits = bitcast <2 x i32> %rs1 to i64 + %rs2.ext = zext i32 %rs2 to i64 + %shamt = shl i64 %rs2.ext, 5 + %res.bits = call i64 @llvm.fshr.i64(i64 %rs1.bits, i64 %rd.bits, i64 %shamt) + %res = bitcast i64 %res.bits to <2 x i32> + ret <2 x i32> %res +} >From a2946bd7434b974dea1dce861c2278043d53159c Mon Sep 17 00:00:00 2001 From: XChy <[email protected]> Date: Fri, 23 Oct 2026 20:28:12 +0800 Subject: [PATCH 2/3] [RISCV] Update packed slide test checks after merge --- llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 52 +++++++++++++------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll index 8d26dffca25474..a296ea44138c60 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll @@ -9045,20 +9045,20 @@ define <8 x i8> @test_pslideupx_v8i8(<8 x i8> %rd, <8 x i8> %rs1, i32 %rs2) { ; RV32-NEXT: slli a0, a4, 29 ; RV32-NEXT: srli a6, a0, 31 ; RV32-NEXT: slli a4, a4, 3 -; RV32-NEXT: bnez a6, .LBB513_2 +; RV32-NEXT: bnez a6, .LBB533_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a5, a1 ; RV32-NEXT: slx a5, a0, a4 -; RV32-NEXT: beqz a6, .LBB513_3 -; RV32-NEXT: j .LBB513_4 -; RV32-NEXT: .LBB513_2: +; RV32-NEXT: beqz a6, .LBB533_3 +; RV32-NEXT: j .LBB533_4 +; RV32-NEXT: .LBB533_2: ; RV32-NEXT: mv a0, a3 ; RV32-NEXT: slx a5, a3, a4 -; RV32-NEXT: bnez a6, .LBB513_4 -; RV32-NEXT: .LBB513_3: +; RV32-NEXT: bnez a6, .LBB533_4 +; RV32-NEXT: .LBB533_3: ; RV32-NEXT: mv a2, a3 -; RV32-NEXT: .LBB513_4: +; RV32-NEXT: .LBB533_4: ; RV32-NEXT: slx a0, a2, a4 ; RV32-NEXT: mv a1, a5 ; RV32-NEXT: ret @@ -9083,17 +9083,17 @@ define <8 x i8> @test_pslidedownx_v8i8(<8 x i8> %rd, <8 x i8> %rs1, ; RV32: # %bb.0: ; RV32-NEXT: slli a5, a4, 3 ; RV32-NEXT: andi a6, a5, 32 -; RV32-NEXT: bnez a6, .LBB514_2 +; RV32-NEXT: bnez a6, .LBB534_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a3, a2 ; RV32-NEXT: mv a2, a1 -; RV32-NEXT: .LBB514_2: +; RV32-NEXT: .LBB534_2: ; RV32-NEXT: mv a4, a2 ; RV32-NEXT: srx a4, a3, a5 -; RV32-NEXT: beqz a6, .LBB514_4 +; RV32-NEXT: beqz a6, .LBB534_4 ; RV32-NEXT: # %bb.3: ; RV32-NEXT: mv a0, a1 -; RV32-NEXT: .LBB514_4: +; RV32-NEXT: .LBB534_4: ; RV32-NEXT: srx a0, a2, a5 ; RV32-NEXT: mv a1, a4 ; RV32-NEXT: ret @@ -9120,20 +9120,20 @@ define <4 x i16> @test_pslideupx_v4i16(<4 x i16> %rd, <4 x i16> %rs1, ; RV32-NEXT: slli a0, a4, 30 ; RV32-NEXT: srli a6, a0, 31 ; RV32-NEXT: slli a4, a4, 4 -; RV32-NEXT: bnez a6, .LBB515_2 +; RV32-NEXT: bnez a6, .LBB535_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a5, a1 ; RV32-NEXT: slx a5, a0, a4 -; RV32-NEXT: beqz a6, .LBB515_3 -; RV32-NEXT: j .LBB515_4 -; RV32-NEXT: .LBB515_2: +; RV32-NEXT: beqz a6, .LBB535_3 +; RV32-NEXT: j .LBB535_4 +; RV32-NEXT: .LBB535_2: ; RV32-NEXT: mv a0, a3 ; RV32-NEXT: slx a5, a3, a4 -; RV32-NEXT: bnez a6, .LBB515_4 -; RV32-NEXT: .LBB515_3: +; RV32-NEXT: bnez a6, .LBB535_4 +; RV32-NEXT: .LBB535_3: ; RV32-NEXT: mv a2, a3 -; RV32-NEXT: .LBB515_4: +; RV32-NEXT: .LBB535_4: ; RV32-NEXT: slx a0, a2, a4 ; RV32-NEXT: mv a1, a5 ; RV32-NEXT: ret @@ -9158,17 +9158,17 @@ define <4 x i16> @test_pslidedownx_v4i16(<4 x i16> %rd, <4 x i16> %rs1, ; RV32: # %bb.0: ; RV32-NEXT: slli a5, a4, 4 ; RV32-NEXT: andi a6, a5, 32 -; RV32-NEXT: bnez a6, .LBB516_2 +; RV32-NEXT: bnez a6, .LBB536_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a3, a2 ; RV32-NEXT: mv a2, a1 -; RV32-NEXT: .LBB516_2: +; RV32-NEXT: .LBB536_2: ; RV32-NEXT: mv a4, a2 ; RV32-NEXT: srx a4, a3, a5 -; RV32-NEXT: beqz a6, .LBB516_4 +; RV32-NEXT: beqz a6, .LBB536_4 ; RV32-NEXT: # %bb.3: ; RV32-NEXT: mv a0, a1 -; RV32-NEXT: .LBB516_4: +; RV32-NEXT: .LBB536_4: ; RV32-NEXT: srx a0, a2, a5 ; RV32-NEXT: mv a1, a4 ; RV32-NEXT: ret @@ -9192,11 +9192,11 @@ define <2 x i32> @test_pslideupx_v2i32(<2 x i32> %rd, <2 x i32> %rs1, ; RV32-LABEL: test_pslideupx_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: andi a4, a4, 1 -; RV32-NEXT: beqz a4, .LBB517_2 +; RV32-NEXT: beqz a4, .LBB537_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: mv a0, a3 -; RV32-NEXT: .LBB517_2: +; RV32-NEXT: .LBB537_2: ; RV32-NEXT: ret ; ; RV64-LABEL: test_pslideupx_v2i32: @@ -9219,11 +9219,11 @@ define <2 x i32> @test_pslidedownx_v2i32(<2 x i32> %rd, <2 x i32> %rs1, ; RV32: # %bb.0: ; RV32-NEXT: slli a4, a4, 31 ; RV32-NEXT: srli a4, a4, 26 -; RV32-NEXT: bnez a4, .LBB518_2 +; RV32-NEXT: bnez a4, .LBB538_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a1, a0 -; RV32-NEXT: .LBB518_2: +; RV32-NEXT: .LBB538_2: ; RV32-NEXT: mv a0, a1 ; RV32-NEXT: mv a1, a2 ; RV32-NEXT: ret >From 8b17e411cae073ec5ef1991c27c4eba91c29a5c0 Mon Sep 17 00:00:00 2001 From: XChy <[email protected]> Date: Sat, 24 Oct 2026 12:30:58 +0800 Subject: [PATCH 3/3] update cases --- .../riscv_packed_simd.c | 16 ++---- llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 52 +++++++++---------- 2 files changed, 30 insertions(+), 38 deletions(-) diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 771154a81257dd..365af7c993a5f6 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -6156,33 +6156,25 @@ uint16x2_t test_pslideupx_u16x2(uint16x2_t rd, uint16x2_t rs1, unsigned rs2) { } // CHECK-LABEL: test_pslidedownx_i8x4: -// RV32: srx -// RV64: pack -// RV64: srl +// CHECK: srx int8x4_t test_pslidedownx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) { return __riscv_pslidedownx_i8x4(rd, rs1, rs2); } // CHECK-LABEL: test_pslidedownx_u8x4: -// RV32: srx -// RV64: pack -// RV64: srl +// CHECK: srx uint8x4_t test_pslidedownx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) { return __riscv_pslidedownx_u8x4(rd, rs1, rs2); } // CHECK-LABEL: test_pslidedownx_i16x2: -// RV32: srx -// RV64: pack -// RV64: srl +// CHECK: srx int16x2_t test_pslidedownx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) { return __riscv_pslidedownx_i16x2(rd, rs1, rs2); } // CHECK-LABEL: test_pslidedownx_u16x2: -// RV32: srx -// RV64: pack -// RV64: srl +// CHECK: srx uint16x2_t test_pslidedownx_u16x2(uint16x2_t rd, uint16x2_t rs1, unsigned rs2) { return __riscv_pslidedownx_u16x2(rd, rs1, rs2); } diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll index 033d80be2ca128..45d3e90405f4c2 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll @@ -9092,20 +9092,20 @@ define <8 x i8> @test_pslideupx_v8i8(<8 x i8> %rd, <8 x i8> %rs1, i32 %rs2) { ; RV32-NEXT: slli a0, a4, 29 ; RV32-NEXT: srli a6, a0, 31 ; RV32-NEXT: slli a4, a4, 3 -; RV32-NEXT: bnez a6, .LBB533_2 +; RV32-NEXT: bnez a6, .LBB536_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a5, a1 ; RV32-NEXT: slx a5, a0, a4 -; RV32-NEXT: beqz a6, .LBB533_3 -; RV32-NEXT: j .LBB533_4 -; RV32-NEXT: .LBB533_2: +; RV32-NEXT: beqz a6, .LBB536_3 +; RV32-NEXT: j .LBB536_4 +; RV32-NEXT: .LBB536_2: ; RV32-NEXT: mv a0, a3 ; RV32-NEXT: slx a5, a3, a4 -; RV32-NEXT: bnez a6, .LBB533_4 -; RV32-NEXT: .LBB533_3: +; RV32-NEXT: bnez a6, .LBB536_4 +; RV32-NEXT: .LBB536_3: ; RV32-NEXT: mv a2, a3 -; RV32-NEXT: .LBB533_4: +; RV32-NEXT: .LBB536_4: ; RV32-NEXT: slx a0, a2, a4 ; RV32-NEXT: mv a1, a5 ; RV32-NEXT: ret @@ -9130,17 +9130,17 @@ define <8 x i8> @test_pslidedownx_v8i8(<8 x i8> %rd, <8 x i8> %rs1, ; RV32: # %bb.0: ; RV32-NEXT: slli a5, a4, 3 ; RV32-NEXT: andi a6, a5, 32 -; RV32-NEXT: bnez a6, .LBB534_2 +; RV32-NEXT: bnez a6, .LBB537_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a3, a2 ; RV32-NEXT: mv a2, a1 -; RV32-NEXT: .LBB534_2: +; RV32-NEXT: .LBB537_2: ; RV32-NEXT: mv a4, a2 ; RV32-NEXT: srx a4, a3, a5 -; RV32-NEXT: beqz a6, .LBB534_4 +; RV32-NEXT: beqz a6, .LBB537_4 ; RV32-NEXT: # %bb.3: ; RV32-NEXT: mv a0, a1 -; RV32-NEXT: .LBB534_4: +; RV32-NEXT: .LBB537_4: ; RV32-NEXT: srx a0, a2, a5 ; RV32-NEXT: mv a1, a4 ; RV32-NEXT: ret @@ -9167,20 +9167,20 @@ define <4 x i16> @test_pslideupx_v4i16(<4 x i16> %rd, <4 x i16> %rs1, ; RV32-NEXT: slli a0, a4, 30 ; RV32-NEXT: srli a6, a0, 31 ; RV32-NEXT: slli a4, a4, 4 -; RV32-NEXT: bnez a6, .LBB535_2 +; RV32-NEXT: bnez a6, .LBB538_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a5, a1 ; RV32-NEXT: slx a5, a0, a4 -; RV32-NEXT: beqz a6, .LBB535_3 -; RV32-NEXT: j .LBB535_4 -; RV32-NEXT: .LBB535_2: +; RV32-NEXT: beqz a6, .LBB538_3 +; RV32-NEXT: j .LBB538_4 +; RV32-NEXT: .LBB538_2: ; RV32-NEXT: mv a0, a3 ; RV32-NEXT: slx a5, a3, a4 -; RV32-NEXT: bnez a6, .LBB535_4 -; RV32-NEXT: .LBB535_3: +; RV32-NEXT: bnez a6, .LBB538_4 +; RV32-NEXT: .LBB538_3: ; RV32-NEXT: mv a2, a3 -; RV32-NEXT: .LBB535_4: +; RV32-NEXT: .LBB538_4: ; RV32-NEXT: slx a0, a2, a4 ; RV32-NEXT: mv a1, a5 ; RV32-NEXT: ret @@ -9205,17 +9205,17 @@ define <4 x i16> @test_pslidedownx_v4i16(<4 x i16> %rd, <4 x i16> %rs1, ; RV32: # %bb.0: ; RV32-NEXT: slli a5, a4, 4 ; RV32-NEXT: andi a6, a5, 32 -; RV32-NEXT: bnez a6, .LBB536_2 +; RV32-NEXT: bnez a6, .LBB539_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a3, a2 ; RV32-NEXT: mv a2, a1 -; RV32-NEXT: .LBB536_2: +; RV32-NEXT: .LBB539_2: ; RV32-NEXT: mv a4, a2 ; RV32-NEXT: srx a4, a3, a5 -; RV32-NEXT: beqz a6, .LBB536_4 +; RV32-NEXT: beqz a6, .LBB539_4 ; RV32-NEXT: # %bb.3: ; RV32-NEXT: mv a0, a1 -; RV32-NEXT: .LBB536_4: +; RV32-NEXT: .LBB539_4: ; RV32-NEXT: srx a0, a2, a5 ; RV32-NEXT: mv a1, a4 ; RV32-NEXT: ret @@ -9239,11 +9239,11 @@ define <2 x i32> @test_pslideupx_v2i32(<2 x i32> %rd, <2 x i32> %rs1, ; RV32-LABEL: test_pslideupx_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: andi a4, a4, 1 -; RV32-NEXT: beqz a4, .LBB537_2 +; RV32-NEXT: beqz a4, .LBB540_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: mv a0, a3 -; RV32-NEXT: .LBB537_2: +; RV32-NEXT: .LBB540_2: ; RV32-NEXT: ret ; ; RV64-LABEL: test_pslideupx_v2i32: @@ -9266,11 +9266,11 @@ define <2 x i32> @test_pslidedownx_v2i32(<2 x i32> %rd, <2 x i32> %rs1, ; RV32: # %bb.0: ; RV32-NEXT: slli a4, a4, 31 ; RV32-NEXT: srli a4, a4, 26 -; RV32-NEXT: bnez a4, .LBB538_2 +; RV32-NEXT: bnez a4, .LBB541_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a1, a0 -; RV32-NEXT: .LBB538_2: +; RV32-NEXT: .LBB541_2: ; RV32-NEXT: mv a0, a1 ; RV32-NEXT: mv a1, a2 ; RV32-NEXT: ret _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
