Author: Dao Bo (Danny) Yang Date: 2026-10-23T15:16:16-07:00 New Revision: d70f4f7d31b3cb744f31f6507f67ae0068aa7f9c
URL: https://github.com/llvm/llvm-project/commit/d70f4f7d31b3cb744f31f6507f67ae0068aa7f9c DIFF: https://github.com/llvm/llvm-project/commit/d70f4f7d31b3cb744f31f6507f67ae0068aa7f9c.diff LOG: [CIR] pmovdb512_mask, pmovdw512_mask, pmovqw512_mask (#213571) Issue #167765 Add CIR handling for pmovdb512_mask, pmovdw512_mask, pmovqw512_mask. Added: Modified: clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c Removed: ################################################################################ diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 35d1b67563df62..970272095d164d 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -1986,6 +1986,34 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { return emitX86Select(builder, getLoc(expr->getExprLoc()), ops[2], Res, ops[1]); } + case X86::BI__builtin_ia32_pmovdb512_mask: + case X86::BI__builtin_ia32_pmovdw512_mask: + case X86::BI__builtin_ia32_pmovqw512_mask: { + // These only require AVX512F, but a byte/word select would need AVX512BW, + // so use the masked intrinsic unless the mask is all ones. + mlir::Location loc = getLoc(expr->getExprLoc()); + auto c = mlir::dyn_cast_or_null<cir::ConstantOp>(ops[2].getDefiningOp()); + if (c && c.isAllOnesValue()) + return builder.createIntCast(ops[0], + cast<cir::VectorType>(ops[1].getType())); + + llvm::StringRef intrinsicName; + switch (builtinID) { + default: + llvm_unreachable("Unsupported intrinsic!"); + case X86::BI__builtin_ia32_pmovdb512_mask: + intrinsicName = "x86.avx512.mask.pmov.db.512"; + break; + case X86::BI__builtin_ia32_pmovdw512_mask: + intrinsicName = "x86.avx512.mask.pmov.dw.512"; + break; + case X86::BI__builtin_ia32_pmovqw512_mask: + intrinsicName = "x86.avx512.mask.pmov.qw.512"; + break; + } + return builder.emitIntrinsicCallOp(loc, intrinsicName, ops[1].getType(), + ops); + } case X86::BI__builtin_ia32_pblendw128: case X86::BI__builtin_ia32_blendpd: case X86::BI__builtin_ia32_blendps: diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c index 819b0d3b2e17e0..f088885e877389 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c @@ -1049,7 +1049,7 @@ int test_mm512_kortestz(__mmask16 __A, __mmask16 __B) { } __m256i test_mm512_cvtepi64_epi32(__m512i __A) { - // CIR-LABEL: test_mm512_cvtepi64_epi32 + // CIR-LABEL: _mm512_cvtepi64_epi32 // CIR: %[[TRUNC:.*]] = cir.cast integral {{.*}} : !cir.vector<8 x !s64i> -> !cir.vector<8 x !s32i> // CIR: %[[RETBC:.*]] = cir.cast bitcast {{.*}} : !cir.vector<8 x !s32i> -> !cir.vector<4 x !s64i> // CIR: cir.store %[[RETBC]], %[[RETPTR:.*]] : !cir.vector<4 x !s64i>, !cir.ptr<!cir.vector<4 x !s64i>> @@ -1066,6 +1066,142 @@ __m256i test_mm512_cvtepi64_epi32(__m512i __A) { return _mm512_cvtepi64_epi32(__A); } +__m128i test_mm512_cvtepi32_epi8(__m512i a) { + // CIR-LABEL: _mm512_cvtepi32_epi8 + // CIR: cir.cast integral {{.*}} : + // CIR-SAME: !cir.vector<16 x !s32i> -> !cir.vector<16 x !s8i> + // + // LLVM-LABEL: test_mm512_cvtepi32_epi8 + // LLVM: trunc <16 x i32> %{{.*}} to <16 x i8> + // + // OGCG-LABEL: test_mm512_cvtepi32_epi8 + // OGCG: trunc <16 x i32> %{{.*}} to <16 x i8> + return _mm512_cvtepi32_epi8(a); +} + +__m128i test_mm512_mask_cvtepi32_epi8(__m128i src, __mmask16 k, + __m512i a) { + // CIR-LABEL: _mm512_mask_cvtepi32_epi8 + // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.pmov.db.512" %{{.*}}, %{{.*}}, %{{.*}} : + // CIR-SAME: (!cir.vector<16 x !s32i>, !cir.vector<16 x !s8i>, !u16i) -> !cir.vector<16 x !s8i> + // + // LLVM-LABEL: test_mm512_mask_cvtepi32_epi8 + // LLVM: call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> %{{.*}}, <16 x i8> %{{.*}}, i16 %{{.*}}) + // + // OGCG-LABEL: test_mm512_mask_cvtepi32_epi8 + // OGCG: call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> %{{.*}}, <16 x i8> %{{.*}}, i16 %{{.*}}) + return _mm512_mask_cvtepi32_epi8(src, k, a); +} + +__m128i test_mm512_maskz_cvtepi32_epi8(__mmask16 k, __m512i a) { + // CIR-LABEL: _mm512_maskz_cvtepi32_epi8 + // CIR: %[[ZERO:.*]] = cir.call @{{.*}}_mm_setzero_si128 + // CIR: %[[ZERO_CAST:.*]] = cir.cast bitcast %[[ZERO]] + // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.pmov.db.512" %{{.*}}, %[[ZERO_CAST]], %{{.*}} : + // CIR-SAME: (!cir.vector<16 x !s32i>, !cir.vector<16 x !s8i>, !u16i) -> !cir.vector<16 x !s8i> + // + // LLVM-LABEL: test_mm512_maskz_cvtepi32_epi8 + // LLVM: store <2 x i64> zeroinitializer + // LLVM: %[[ZERO:.*]] = bitcast <2 x i64> %{{.*}} to <16 x i8> + // LLVM: call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> %{{.*}}, <16 x i8> %[[ZERO]], i16 %{{.*}}) + // + // OGCG-LABEL: test_mm512_maskz_cvtepi32_epi8 + // OGCG: store <2 x i64> zeroinitializer + // OGCG: %[[ZERO:.*]] = bitcast <2 x i64> %{{.*}} to <16 x i8> + // OGCG: call <16 x i8> @llvm.x86.avx512.mask.pmov.db.512(<16 x i32> %{{.*}}, <16 x i8> %[[ZERO]], i16 %{{.*}}) + return _mm512_maskz_cvtepi32_epi8(k, a); +} + +__m256i test_mm512_cvtepi32_epi16(__m512i a) { + // CIR-LABEL: _mm512_cvtepi32_epi16 + // CIR: cir.cast integral {{.*}} : + // CIR-SAME: !cir.vector<16 x !s32i> -> !cir.vector<16 x !s16i> + // + // LLVM-LABEL: test_mm512_cvtepi32_epi16 + // LLVM: trunc <16 x i32> %{{.*}} to <16 x i16> + // + // OGCG-LABEL: test_mm512_cvtepi32_epi16 + // OGCG: trunc <16 x i32> %{{.*}} to <16 x i16> + return _mm512_cvtepi32_epi16(a); +} + +__m256i test_mm512_mask_cvtepi32_epi16(__m256i src, __mmask16 k, __m512i a) { + // CIR-LABEL: _mm512_mask_cvtepi32_epi16 + // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.pmov.dw.512" %{{.*}}, %{{.*}}, %{{.*}} : + // CIR-SAME: (!cir.vector<16 x !s32i>, !cir.vector<16 x !s16i>, !u16i) -> !cir.vector<16 x !s16i> + // + // LLVM-LABEL: test_mm512_mask_cvtepi32_epi16 + // LLVM: call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> %{{.*}}, <16 x i16> %{{.*}}, i16 %{{.*}}) + // + // OGCG-LABEL: test_mm512_mask_cvtepi32_epi16 + // OGCG: call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> %{{.*}}, <16 x i16> %{{.*}}, i16 %{{.*}}) + return _mm512_mask_cvtepi32_epi16(src, k, a); +} + +__m256i test_mm512_maskz_cvtepi32_epi16(__mmask16 k, __m512i a) { + // CIR-LABEL: _mm512_maskz_cvtepi32_epi16 + // CIR: %[[ZERO:.*]] = cir.call @{{.*}}_mm256_setzero_si256 + // CIR: %[[ZERO_CAST:.*]] = cir.cast bitcast %[[ZERO]] + // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.pmov.dw.512" %{{.*}}, %[[ZERO_CAST]], %{{.*}} : + // CIR-SAME: (!cir.vector<16 x !s32i>, !cir.vector<16 x !s16i>, !u16i) -> !cir.vector<16 x !s16i> + // + // LLVM-LABEL: test_mm512_maskz_cvtepi32_epi16 + // LLVM: store <4 x i64> zeroinitializer + // LLVM: %[[ZERO:.*]] = bitcast <4 x i64> %{{.*}} to <16 x i16> + // LLVM: call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> %{{.*}}, <16 x i16> %[[ZERO]], i16 %{{.*}}) + // + // OGCG-LABEL: test_mm512_maskz_cvtepi32_epi16 + // OGCG: store <4 x i64> zeroinitializer + // OGCG: %[[ZERO:.*]] = bitcast <4 x i64> %{{.*}} to <16 x i16> + // OGCG: call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> %{{.*}}, <16 x i16> %[[ZERO]], i16 %{{.*}}) + return _mm512_maskz_cvtepi32_epi16(k, a); +} + +__m128i test_mm512_cvtepi64_epi16(__m512i a) { + // CIR-LABEL: _mm512_cvtepi64_epi16 + // CIR: cir.cast integral {{.*}} : + // CIR-SAME: !cir.vector<8 x !s64i> -> !cir.vector<8 x !s16i> + // + // LLVM-LABEL: test_mm512_cvtepi64_epi16 + // LLVM: trunc <8 x i64> %{{.*}} to <8 x i16> + // + // OGCG-LABEL: test_mm512_cvtepi64_epi16 + // OGCG: trunc <8 x i64> %{{.*}} to <8 x i16> + return _mm512_cvtepi64_epi16(a); +} + +__m128i test_mm512_mask_cvtepi64_epi16(__m128i src, __mmask8 k, __m512i a) { + // CIR-LABEL: _mm512_mask_cvtepi64_epi16 + // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.pmov.qw.512" %{{.*}}, %{{.*}}, %{{.*}} : + // CIR-SAME: (!cir.vector<8 x !s64i>, !cir.vector<8 x !s16i>, !u8i) -> !cir.vector<8 x !s16i> + // + // LLVM-LABEL: test_mm512_mask_cvtepi64_epi16 + // LLVM: call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %{{.*}}, <8 x i16> %{{.*}}, i8 %{{.*}}) + // + // OGCG-LABEL: test_mm512_mask_cvtepi64_epi16 + // OGCG: call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %{{.*}}, <8 x i16> %{{.*}}, i8 %{{.*}}) + return _mm512_mask_cvtepi64_epi16(src, k, a); +} + +__m128i test_mm512_maskz_cvtepi64_epi16(__mmask8 k, __m512i a) { + // CIR-LABEL: _mm512_maskz_cvtepi64_epi16 + // CIR: %[[ZERO:.*]] = cir.call @{{.*}}_mm_setzero_si128 + // CIR: %[[ZERO_CAST:.*]] = cir.cast bitcast %[[ZERO]] + // CIR: cir.call_llvm_intrinsic "x86.avx512.mask.pmov.qw.512" %{{.*}}, %[[ZERO_CAST]], %{{.*}} : + // CIR-SAME: (!cir.vector<8 x !s64i>, !cir.vector<8 x !s16i>, !u8i) -> !cir.vector<8 x !s16i> + // + // LLVM-LABEL: test_mm512_maskz_cvtepi64_epi16 + // LLVM: store <2 x i64> zeroinitializer + // LLVM: %[[ZERO:.*]] = bitcast <2 x i64> %{{.*}} to <8 x i16> + // LLVM: call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %{{.*}}, <8 x i16> %[[ZERO]], i8 %{{.*}}) + // + // OGCG-LABEL: test_mm512_maskz_cvtepi64_epi16 + // OGCG: store <2 x i64> zeroinitializer + // OGCG: %[[ZERO:.*]] = bitcast <2 x i64> %{{.*}} to <8 x i16> + // OGCG: call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %{{.*}}, <8 x i16> %[[ZERO]], i8 %{{.*}}) + return _mm512_maskz_cvtepi64_epi16(k, a); +} + __m256i test_mm512_mask_cvtepi64_epi32(__m256i __O, __mmask8 __M, __m512i __A) { // CIR-LABEL: test_mm512_mask_cvtepi64_epi32 // CIR: %[[TRUNC:.*]] = cir.cast integral {{.*}} : !cir.vector<8 x !s64i> -> !cir.vector<8 x !s32i> _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
