https://github.com/bruteforceboy updated https://github.com/llvm/llvm-project/pull/230083
>From 0a2ee53b04a52bdb564f62b676fd4c306357a7d8 Mon Sep 17 00:00:00 2001 From: bruteforceboy <[email protected]> Date: Wed, 7 Oct 2026 18:14:06 +0800 Subject: [PATCH 1/2] [clang][CIR] Add tests for SVE EORV intrinsics --- .../AArch64/sve-intrinsics/acle_sve_eorv.c | 155 ----------------- clang/test/CodeGen/AArch64/sve/eorv.c | 159 ++++++++++++++++++ 2 files changed, 159 insertions(+), 155 deletions(-) delete mode 100644 clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eorv.c create mode 100644 clang/test/CodeGen/AArch64/sve/eorv.c diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eorv.c b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eorv.c deleted file mode 100644 index ab2ddcd0a7dae..0000000000000 --- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eorv.c +++ /dev/null @@ -1,155 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s -// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s - -#include <arm_sve.h> - -#if defined __ARM_FEATURE_SME -#define MODE_ATTR __arm_streaming -#else -#define MODE_ATTR -#endif - -#ifdef SVE_OVERLOADED_FORMS -// A simple used,unused... macro, long enough to represent any SVE builtin. -#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 -#else -#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 -#endif - -// CHECK-LABEL: @test_sveorv_s8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) -// CHECK-NEXT: ret i8 [[TMP0]] -// -// CPP-CHECK-LABEL: @_Z14test_sveorv_s8u10__SVBool_tu10__SVInt8_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i8 [[TMP0]] -// -int8_t test_sveorv_s8(svbool_t pg, svint8_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(sveorv,_s8,,)(pg, op); -} - -// CHECK-LABEL: @test_sveorv_s16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]]) -// CHECK-NEXT: ret i16 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_sveorv_s16u10__SVBool_tu11__SVInt16_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i16 [[TMP1]] -// -int16_t test_sveorv_s16(svbool_t pg, svint16_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(sveorv,_s16,,)(pg, op); -} - -// CHECK-LABEL: @test_sveorv_s32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CHECK-NEXT: ret i32 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_sveorv_s32u10__SVBool_tu11__SVInt32_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i32 [[TMP1]] -// -int32_t test_sveorv_s32(svbool_t pg, svint32_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(sveorv,_s32,,)(pg, op); -} - -// CHECK-LABEL: @test_sveorv_s64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]]) -// CHECK-NEXT: ret i64 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_sveorv_s64u10__SVBool_tu11__SVInt64_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i64 [[TMP1]] -// -int64_t test_sveorv_s64(svbool_t pg, svint64_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(sveorv,_s64,,)(pg, op); -} - -// CHECK-LABEL: @test_sveorv_u8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) -// CHECK-NEXT: ret i8 [[TMP0]] -// -// CPP-CHECK-LABEL: @_Z14test_sveorv_u8u10__SVBool_tu11__SVUint8_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i8 [[TMP0]] -// -uint8_t test_sveorv_u8(svbool_t pg, svuint8_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(sveorv,_u8,,)(pg, op); -} - -// CHECK-LABEL: @test_sveorv_u16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]]) -// CHECK-NEXT: ret i16 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_sveorv_u16u10__SVBool_tu12__SVUint16_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i16 [[TMP1]] -// -uint16_t test_sveorv_u16(svbool_t pg, svuint16_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(sveorv,_u16,,)(pg, op); -} - -// CHECK-LABEL: @test_sveorv_u32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CHECK-NEXT: ret i32 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_sveorv_u32u10__SVBool_tu12__SVUint32_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i32 [[TMP1]] -// -uint32_t test_sveorv_u32(svbool_t pg, svuint32_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(sveorv,_u32,,)(pg, op); -} - -// CHECK-LABEL: @test_sveorv_u64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]]) -// CHECK-NEXT: ret i64 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_sveorv_u64u10__SVBool_tu12__SVUint64_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i64 [[TMP1]] -// -uint64_t test_sveorv_u64(svbool_t pg, svuint64_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(sveorv,_u64,,)(pg, op); -} diff --git a/clang/test/CodeGen/AArch64/sve/eorv.c b/clang/test/CodeGen/AArch64/sve/eorv.c new file mode 100644 index 0000000000000..463321efb739b --- /dev/null +++ b/clang/test/CodeGen/AArch64/sve/eorv.c @@ -0,0 +1,159 @@ +// REQUIRES: aarch64-registered-target + +// DEFINE: %{optimize} = opt -passes=mem2reg,tailcallelim -S + +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %} + +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM %} + +// RUN: %clang_cc1_cg_arm64_sve -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM +// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM +// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM + +// RUN: %clang_cc1_cg_arm64_sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s + +//============================================================================= +// NOTES +// +// Tests for SVE EORV intrinsics +//============================================================================= + +#include <arm_sve.h> + +#if defined __ARM_FEATURE_SME +#define MODE_ATTR __arm_streaming +#else +#define MODE_ATTR +#endif + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + +// C-LABEL: @test_sveorv_s8( +// CPP-LABEL: @_Z14test_sveorv_s8u10__SVBool_tu10__SVInt8_t( +int8_t test_sveorv_s8(svbool_t pg, svint8_t op) MODE_ATTR +{ +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.eorv" %{{.*}}, %{{.*}} : +// CIR-SAME: -> !s8i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[OP]]) +// LLVM: ret i8 [[TMP0]] + return SVE_ACLE_FUNC(sveorv,_s8,,)(pg, op); +} + +// C-LABEL: @test_sveorv_s16( +// CPP-LABEL: @_Z15test_sveorv_s16u10__SVBool_tu11__SVInt16_t( +int16_t test_sveorv_s16(svbool_t pg, svint16_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[8] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.eorv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !s16i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 8 x i16> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP]]) +// LLVM: ret i16 [[TMP1]] + return SVE_ACLE_FUNC(sveorv,_s16,,)(pg, op); +} + +// C-LABEL: @test_sveorv_s32( +// CPP-LABEL: @_Z15test_sveorv_s32u10__SVBool_tu11__SVInt32_t( +int32_t test_sveorv_s32(svbool_t pg, svint32_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[4] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.eorv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !s32i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP]]) +// LLVM: ret i32 [[TMP1]] + return SVE_ACLE_FUNC(sveorv,_s32,,)(pg, op); +} + +// C-LABEL: @test_sveorv_s64( +// CPP-LABEL: @_Z15test_sveorv_s64u10__SVBool_tu11__SVInt64_t( +int64_t test_sveorv_s64(svbool_t pg, svint64_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[2] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.eorv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !s64i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 2 x i64> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP]]) +// LLVM: ret i64 [[TMP1]] + return SVE_ACLE_FUNC(sveorv,_s64,,)(pg, op); +} + +// C-LABEL: @test_sveorv_u8( +// CPP-LABEL: @_Z14test_sveorv_u8u10__SVBool_tu11__SVUint8_t( +uint8_t test_sveorv_u8(svbool_t pg, svuint8_t op) MODE_ATTR +{ +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.eorv" %{{.*}}, %{{.*}} : +// CIR-SAME: -> !u8i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[OP]]) +// LLVM: ret i8 [[TMP0]] + return SVE_ACLE_FUNC(sveorv,_u8,,)(pg, op); +} + +// C-LABEL: @test_sveorv_u16( +// CPP-LABEL: @_Z15test_sveorv_u16u10__SVBool_tu12__SVUint16_t( +uint16_t test_sveorv_u16(svbool_t pg, svuint16_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[8] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.eorv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !u16i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 8 x i16> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP]]) +// LLVM: ret i16 [[TMP1]] + return SVE_ACLE_FUNC(sveorv,_u16,,)(pg, op); +} + +// C-LABEL: @test_sveorv_u32( +// CPP-LABEL: @_Z15test_sveorv_u32u10__SVBool_tu12__SVUint32_t( +uint32_t test_sveorv_u32(svbool_t pg, svuint32_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[4] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.eorv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !u32i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP]]) +// LLVM: ret i32 [[TMP1]] + return SVE_ACLE_FUNC(sveorv,_u32,,)(pg, op); +} + +// C-LABEL: @test_sveorv_u64( +// CPP-LABEL: @_Z15test_sveorv_u64u10__SVBool_tu12__SVUint64_t( +uint64_t test_sveorv_u64(svbool_t pg, svuint64_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[2] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.eorv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !u64i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 2 x i64> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP]]) +// LLVM: ret i64 [[TMP1]] + return SVE_ACLE_FUNC(sveorv,_u64,,)(pg, op); +} >From af20b77128f2cfcee8bb6973dd09a701ce07668a Mon Sep 17 00:00:00 2001 From: bruteforceboy <[email protected]> Date: Sun, 11 Oct 2026 02:44:51 +0800 Subject: [PATCH 2/2] Apply review comment: drop tailcallelim --- clang/test/CodeGen/AArch64/sve/eorv.c | 30 +++++++++++++-------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/clang/test/CodeGen/AArch64/sve/eorv.c b/clang/test/CodeGen/AArch64/sve/eorv.c index 463321efb739b..011324195f583 100644 --- a/clang/test/CodeGen/AArch64/sve/eorv.c +++ b/clang/test/CodeGen/AArch64/sve/eorv.c @@ -1,6 +1,6 @@ // REQUIRES: aarch64-registered-target -// DEFINE: %{optimize} = opt -passes=mem2reg,tailcallelim -S +// DEFINE: %{optimize} = opt -passes=mem2reg -S // RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %} // RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %} @@ -44,7 +44,7 @@ int8_t test_sveorv_s8(svbool_t pg, svint8_t op) MODE_ATTR // CIR-SAME: -> !s8i // LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) -// LLVM: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[OP]]) +// LLVM: [[TMP0:%.*]] = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[OP]]) // LLVM: ret i8 [[TMP0]] return SVE_ACLE_FUNC(sveorv,_s8,,)(pg, op); } @@ -59,8 +59,8 @@ int16_t test_sveorv_s16(svbool_t pg, svint16_t op) MODE_ATTR // CIR-SAME: -> !s16i // LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 8 x i16> [[OP:%.*]]) -// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]]) -// LLVM: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP]]) +// LLVM: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP]]) // LLVM: ret i16 [[TMP1]] return SVE_ACLE_FUNC(sveorv,_s16,,)(pg, op); } @@ -75,8 +75,8 @@ int32_t test_sveorv_s32(svbool_t pg, svint32_t op) MODE_ATTR // CIR-SAME: -> !s32i // LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]]) -// LLVM: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) -// LLVM: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP]]) +// LLVM: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP]]) // LLVM: ret i32 [[TMP1]] return SVE_ACLE_FUNC(sveorv,_s32,,)(pg, op); } @@ -91,8 +91,8 @@ int64_t test_sveorv_s64(svbool_t pg, svint64_t op) MODE_ATTR // CIR-SAME: -> !s64i // LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 2 x i64> [[OP:%.*]]) -// LLVM: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]]) -// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP]]) +// LLVM: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP]]) // LLVM: ret i64 [[TMP1]] return SVE_ACLE_FUNC(sveorv,_s64,,)(pg, op); } @@ -105,7 +105,7 @@ uint8_t test_sveorv_u8(svbool_t pg, svuint8_t op) MODE_ATTR // CIR-SAME: -> !u8i // LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) -// LLVM: [[TMP0:%.*]] = tail call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[OP]]) +// LLVM: [[TMP0:%.*]] = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[OP]]) // LLVM: ret i8 [[TMP0]] return SVE_ACLE_FUNC(sveorv,_u8,,)(pg, op); } @@ -120,8 +120,8 @@ uint16_t test_sveorv_u16(svbool_t pg, svuint16_t op) MODE_ATTR // CIR-SAME: -> !u16i // LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 8 x i16> [[OP:%.*]]) -// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]]) -// LLVM: [[TMP1:%.*]] = tail call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP]]) +// LLVM: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP]]) // LLVM: ret i16 [[TMP1]] return SVE_ACLE_FUNC(sveorv,_u16,,)(pg, op); } @@ -136,8 +136,8 @@ uint32_t test_sveorv_u32(svbool_t pg, svuint32_t op) MODE_ATTR // CIR-SAME: -> !u32i // LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]]) -// LLVM: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) -// LLVM: [[TMP1:%.*]] = tail call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP]]) +// LLVM: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP]]) // LLVM: ret i32 [[TMP1]] return SVE_ACLE_FUNC(sveorv,_u32,,)(pg, op); } @@ -152,8 +152,8 @@ uint64_t test_sveorv_u64(svbool_t pg, svuint64_t op) MODE_ATTR // CIR-SAME: -> !u64i // LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 2 x i64> [[OP:%.*]]) -// LLVM: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]]) -// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP]]) +// LLVM: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP]]) // LLVM: ret i64 [[TMP1]] return SVE_ACLE_FUNC(sveorv,_u64,,)(pg, op); } _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
