https://github.com/artagnon created https://github.com/llvm/llvm-project/pull/229718
Use --instruction-tables=full uniformly in llvm-mca tests, and migrate the clang-driver test to a print-enabled-extensions test. Assisted-by: llm >From e6c4e4d303d97589321bff632bfbee2ba4c5b44b Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra <[email protected]> Date: Wed, 7 Oct 2026 10:41:48 +0100 Subject: [PATCH] [RISCV] Modernize tests for tt-ascalon-x (NFC) Use --instruction-tables=full uniformly in llvm-mca tests, and migrate the clang-driver test to a print-enabled-extensions test. Assisted-by: llm --- .../riscv-tt-ascalon-x.c | 106 ++++++++++++++++++ clang/test/Driver/riscv-cpus.c | 71 ------------ .../tools/llvm-mca/RISCV/tt-ascalon-x/fp.s | 79 +++++++------ .../tools/llvm-mca/RISCV/tt-ascalon-x/fx.s | 67 ++++++----- .../llvm-mca/RISCV/tt-ascalon-x/vdiv_vsqrt.s | 2 +- .../llvm-mca/RISCV/tt-ascalon-x/vislide-vx.s | 2 +- .../llvm-mca/RISCV/tt-ascalon-x/vle-vse-vlm.s | 2 +- .../llvm-mca/RISCV/tt-ascalon-x/vlse-vsse.s | 2 +- .../llvm-mca/RISCV/tt-ascalon-x/vlseg-vsseg.s | 2 +- .../llvm-mca/RISCV/tt-ascalon-x/vlxe-vsxe.s | 2 +- .../tools/llvm-mca/RISCV/tt-ascalon-x/vmv.s | 2 +- .../llvm-mca/RISCV/tt-ascalon-x/vreduce.s | 2 +- .../RISCV/tt-ascalon-x/vrgather-vcompress.s | 2 +- .../llvm-mca/RISCV/tt-ascalon-x/vshift-vmul.s | 2 +- 14 files changed, 196 insertions(+), 147 deletions(-) create mode 100644 clang/test/Driver/print-enabled-extensions/riscv-tt-ascalon-x.c diff --git a/clang/test/Driver/print-enabled-extensions/riscv-tt-ascalon-x.c b/clang/test/Driver/print-enabled-extensions/riscv-tt-ascalon-x.c new file mode 100644 index 00000000000000..69707ec8e2fe00 --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/riscv-tt-ascalon-x.c @@ -0,0 +1,106 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang --target=riscv64 -mcpu=tt-ascalon-x --print-enabled-extensions | FileCheck %s + +// CHECK: Extensions enabled for the given RISC-V target +// CHECK-EMPTY: +// CHECK-NEXT: Name Version Description +// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set) +// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division) +// CHECK-NEXT: a 2.1 'A' (Atomic Instructions) +// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) +// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) +// CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) +// CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors) +// CHECK-NEXT: h 1.0 'H' (Hypervisor) +// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes) +// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions) +// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions) +// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions) +// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A) +// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement) +// CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores) +// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences) +// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers) +// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) +// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) +// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) +// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints) +// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint) +// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters) +// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations) +// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) +// CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set Size of at Most 64 Bytes) +// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations) +// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) +// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set) +// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point) +// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts) +// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point) +// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) +// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions) +// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) +// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: zkr 1.0 'Zkr' (Entropy Source Extension) +// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) +// CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic bit-manipulation instructions) +// CHECK-NEXT: zvbc 1.0 'Zvbc' (Vector Carryless Multiplication) +// CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension) +// CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW) +// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension) +// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension) +// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW) +// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16 Converts) +// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add) +// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point) +// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zvkb 1.0 'Zvkb' (Vector Bit-manipulation used in Cryptography) +// CHECK-NEXT: zvkg 1.0 'Zvkg' (Vector GCM instructions for Cryptography) +// CHECK-NEXT: zvkn 1.0 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt') +// CHECK-NEXT: zvknc 1.0 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc') +// CHECK-NEXT: zvkned 1.0 'Zvkned' (Vector AES Encryption & Decryption (Single Round)) +// CHECK-NEXT: zvkng 1.0 'Zvkng' (shorthand for 'Zvkn' and 'Zvkg') +// CHECK-NEXT: zvknha 1.0 'Zvknha' (Vector SHA-2 (SHA-256 only)) +// CHECK-NEXT: zvknhb 1.0 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512)) +// CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector Data-Independent Execution Latency) +// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128) +// CHECK-NEXT: zvl256b 1.0 'Zvl256b' (Minimum Vector Length 256) +// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32) +// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64) +// CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor) +// CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero) +// CHECK-NEXT: shgatpa 1.0 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare) +// CHECK-NEXT: shtvala 1.0 'Shtvala' (htval provides all needed values) +// CHECK-NEXT: shvsatpa 1.0 'Shvsatpa' (vsatp supports all modes supported by satp) +// CHECK-NEXT: shvstvala 1.0 'Shvstvala' (vstval provides all needed values) +// CHECK-NEXT: shvstvecd 1.0 'Shvstvecd' (vstvec supports Direct mode) +// CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level) +// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode) +// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode) +// CHECK-NEXT: smrnmi 1.0 'Smrnmi' (Resumable Non-Maskable Interrupts) +// CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension) +// CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level) +// CHECK-NEXT: ssccptr 1.0 'Ssccptr' (Main memory supports page table reads) +// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering) +// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero) +// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode) +// CHECK-NEXT: ssstateen 1.0 'Ssstateen' (Supervisor-mode view of the state-enable extension) +// CHECK-NEXT: ssstrict 1.0 'Ssstrict' (No non-conforming extensions are present) +// CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts) +// CHECK-NEXT: sstvala 1.0 'Sstvala' (stval provides all needed values) +// CHECK-NEXT: sstvecd 1.0 'Sstvecd' (stvec supports Direct mode) +// CHECK-NEXT: ssu64xl 1.0 'Ssu64xl' (UXLEN=64 supported) +// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking) +// CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits) +// CHECK-NEXT: svbare 1.0 'Svbare' (satp mode Bare supported) +// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation) +// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity) +// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types) +// CHECK-EMPTY: +// CHECK-NEXT: Experimental extensions +// CHECK-EMPTY: +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkr1p0_zkt1p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_smaia1p0_smmpm1p0_smnpm1p0_smrnmi1p0_smstateen1p0_ssaia1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_ssstrict1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0 diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 9cfe399ca71a7a..783622d3e1f7f4 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -179,77 +179,6 @@ // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s // MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalon-x | FileCheck -check-prefix=MTUNE-TT-ASCALON-X %s -// MTUNE-TT-ASCALON-X: "-tune-cpu" "tt-ascalon-x" - -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=tt-ascalon-x | FileCheck -check-prefix=MCPU-TT-ASCALON-X %s -// MCPU-TT-ASCALON-X: "-target-cpu" "tt-ascalon-x" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+m" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+a" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+f" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+d" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+c" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+v" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+h" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicbom" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicbop" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicboz" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicntr" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicond" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicsr" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zifencei" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zihintntl" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zihintpause" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zihpm" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zimop" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zmmul" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zawrs" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zfa" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zfbfmin" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zfh" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zfhmin" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zca" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zcb" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zba" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zbb" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zbs" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zkr" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zkt" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvbb" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvbc" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zve32f" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zve32x" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zve64d" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zve64f" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zve64x" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvfbfmin" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvfbfwma" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvfh" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvfhmin" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkb" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkg" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkn" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvknc" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkned" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkng" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvknha" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvknhb" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkt" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvl128b" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvl256b" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvl32b" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvl64b" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+smaia" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+smmpm" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+smnpm" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+smrnmi" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+smstateen" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+sscofpmf" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+svinval" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+svnapot" -// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+svpbmt" -// MCPU-TT-ASCALON-X-SAME: "-target-abi" "lp64d" - // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s // MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu" diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fp.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fp.s index be22f31b9d690e..0fb9250630626e 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fp.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fp.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=tt-ascalon-x --iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s fmin.s ft0, fa0, fa1 fmax.s ft1, fa0, fa1 @@ -14,15 +14,19 @@ fdiv.d fs4, fa3, ft5 fsqrt.s ft1, fa2 fsqrt.d ft2, fa3 -# CHECK: Iterations: 1 -# CHECK-NEXT: Instructions: 12 -# CHECK-NEXT: Total Cycles: 31 -# CHECK-NEXT: Total uOps: 12 - -# CHECK: Dispatch Width: 8 -# CHECK-NEXT: uOps Per Cycle: 0.39 -# CHECK-NEXT: IPC: 0.39 -# CHECK-NEXT: Block RThroughput: 23.0 +# CHECK: Resources: +# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB +# CHECK-NEXT: [1] - AscalonFPA:1 +# CHECK-NEXT: [2] - AscalonFPB:1 +# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD +# CHECK-NEXT: [4] - AscalonFXA:1 +# CHECK-NEXT: [5] - AscalonFXB:1 +# CHECK-NEXT: [6] - AscalonFXC:2 +# CHECK-NEXT: [7] - AscalonFXD:2 +# CHECK-NEXT: [8] - AscalonLS:3 +# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB +# CHECK-NEXT: [10] - AscalonVA:1 +# CHECK-NEXT: [11] - AscalonVB:1 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -31,20 +35,23 @@ fsqrt.d ft2, fa3 # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) +# CHECK-NEXT: [7]: Bypass Latency +# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle]) +# CHECK-NEXT: [9]: LLVM Opcode Name -# CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 0.50 fmin.s ft0, fa0, fa1 -# CHECK-NEXT: 1 3 0.50 fmax.s ft1, fa0, fa1 -# CHECK-NEXT: 1 3 0.50 fmin.d ft2, ft4, ft5 -# CHECK-NEXT: 1 3 0.50 fmax.d ft3, ft4, ft5 -# CHECK-NEXT: 1 3 0.50 fmadd.s fs0, fs0, fs8, fs9 -# CHECK-NEXT: 1 3 0.50 fmsub.s fs1, fs1, fs8, fs9 -# CHECK-NEXT: 1 3 0.50 fmul.s fs3, fs3, fs4 -# CHECK-NEXT: 1 7 3.50 fdiv.s fs2, fs3, fs4 -# CHECK-NEXT: 1 3 0.50 fmul.d ft4, ft4, ft5 -# CHECK-NEXT: 1 12 6.00 fdiv.d fs4, fa3, ft5 -# CHECK-NEXT: 1 7 3.50 fsqrt.s ft1, fa2 -# CHECK-NEXT: 1 12 6.00 fsqrt.d ft2, fa3 +# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: 1 3 0.50 3 AscalonFP FMIN_S fmin.s ft0, fa0, fa1 +# CHECK-NEXT: 1 3 0.50 3 AscalonFP FMAX_S fmax.s ft1, fa0, fa1 +# CHECK-NEXT: 1 3 0.50 3 AscalonFP FMIN_D fmin.d ft2, ft4, ft5 +# CHECK-NEXT: 1 3 0.50 3 AscalonFP FMAX_D fmax.d ft3, ft4, ft5 +# CHECK-NEXT: 1 3 0.50 3 AscalonFP FMADD_S fmadd.s fs0, fs0, fs8, fs9 +# CHECK-NEXT: 1 3 0.50 3 AscalonFP FMSUB_S fmsub.s fs1, fs1, fs8, fs9 +# CHECK-NEXT: 1 3 0.50 3 AscalonFP FMUL_S fmul.s fs3, fs3, fs4 +# CHECK-NEXT: 1 7 3.50 7 AscalonFP[7] FDIV_S fdiv.s fs2, fs3, fs4 +# CHECK-NEXT: 1 3 0.50 3 AscalonFP FMUL_D fmul.d ft4, ft4, ft5 +# CHECK-NEXT: 1 12 6.00 12 AscalonFP[12] FDIV_D fdiv.d fs4, fa3, ft5 +# CHECK-NEXT: 1 7 3.50 7 AscalonFP[7] FSQRT_S fsqrt.s ft1, fa2 +# CHECK-NEXT: 1 12 6.00 12 AscalonFP[12] FSQRT_D fsqrt.d ft2, fa3 # CHECK: Resources: # CHECK-NEXT: [0] - AscalonFPA @@ -63,19 +70,19 @@ fsqrt.d ft2, fa3 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] -# CHECK-NEXT: 18.00 28.00 - - - - - - - - - - - +# CHECK-NEXT: 23.00 23.00 - - - - - - - - - - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions: -# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmin.s ft0, fa0, fa1 -# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmax.s ft1, fa0, fa1 -# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmin.d ft2, ft4, ft5 -# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmax.d ft3, ft4, ft5 -# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmadd.s fs0, fs0, fs8, fs9 -# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmsub.s fs1, fs1, fs8, fs9 -# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmul.s fs3, fs3, fs4 -# CHECK-NEXT: 7.00 - - - - - - - - - - - - fdiv.s fs2, fs3, fs4 -# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmul.d ft4, ft4, ft5 -# CHECK-NEXT: - 12.00 - - - - - - - - - - - fdiv.d fs4, fa3, ft5 -# CHECK-NEXT: 7.00 - - - - - - - - - - - - fsqrt.s ft1, fa2 -# CHECK-NEXT: - 12.00 - - - - - - - - - - - fsqrt.d ft2, fa3 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - fmin.s ft0, fa0, fa1 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - fmax.s ft1, fa0, fa1 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - fmin.d ft2, ft4, ft5 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - fmax.d ft3, ft4, ft5 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - fmadd.s fs0, fs0, fs8, fs9 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - fmsub.s fs1, fs1, fs8, fs9 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - fmul.s fs3, fs3, fs4 +# CHECK-NEXT: 3.50 3.50 - - - - - - - - - - - fdiv.s fs2, fs3, fs4 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - fmul.d ft4, ft4, ft5 +# CHECK-NEXT: 6.00 6.00 - - - - - - - - - - - fdiv.d fs4, fa3, ft5 +# CHECK-NEXT: 3.50 3.50 - - - - - - - - - - - fsqrt.s ft1, fa2 +# CHECK-NEXT: 6.00 6.00 - - - - - - - - - - - fsqrt.d ft2, fa3 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fx.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fx.s index 18c584485e459d..d20f03129d48d5 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fx.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fx.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=tt-ascalon-x --iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s mul t0, a0, t0 sub s2, a2, a3 @@ -14,15 +14,19 @@ fcvt.s.w f1, t3 add s2, s2, s2 fcvt.w.s t5, f3 -# CHECK: Iterations: 1 -# CHECK-NEXT: Instructions: 12 -# CHECK-NEXT: Total Cycles: 22 -# CHECK-NEXT: Total uOps: 12 - -# CHECK: Dispatch Width: 8 -# CHECK-NEXT: uOps Per Cycle: 0.55 -# CHECK-NEXT: IPC: 0.55 -# CHECK-NEXT: Block RThroughput: 17.0 +# CHECK: Resources: +# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB +# CHECK-NEXT: [1] - AscalonFPA:1 +# CHECK-NEXT: [2] - AscalonFPB:1 +# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD +# CHECK-NEXT: [4] - AscalonFXA:1 +# CHECK-NEXT: [5] - AscalonFXB:1 +# CHECK-NEXT: [6] - AscalonFXC:2 +# CHECK-NEXT: [7] - AscalonFXD:2 +# CHECK-NEXT: [8] - AscalonLS:3 +# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB +# CHECK-NEXT: [10] - AscalonVA:1 +# CHECK-NEXT: [11] - AscalonVB:1 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -31,20 +35,23 @@ fcvt.w.s t5, f3 # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) +# CHECK-NEXT: [7]: Bypass Latency +# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle]) +# CHECK-NEXT: [9]: LLVM Opcode Name -# CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 mul t0, a0, t0 -# CHECK-NEXT: 1 1 0.17 sub s2, a2, a3 -# CHECK-NEXT: 1 7 7.00 div t1, t2, t3 -# CHECK-NEXT: 1 1 0.17 add t1, a4, gp -# CHECK-NEXT: 1 7 7.00 div a1, a2, a3 -# CHECK-NEXT: 1 1 0.17 add t1, a0, t0 -# CHECK-NEXT: 1 3 1.00 mul s0, s0, a5 -# CHECK-NEXT: 1 1 0.17 add t2, t2, t2 -# CHECK-NEXT: 1 1 0.17 sub s1, s0, s1 -# CHECK-NEXT: 1 1 1.00 fcvt.s.w ft1, t3 -# CHECK-NEXT: 1 1 0.17 add s2, s2, s2 -# CHECK-NEXT: 1 1 1.00 fcvt.w.s t5, ft3 +# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: 1 3 1.00 3 AscalonFX,AscalonFXA MUL mul t0, a0, t0 +# CHECK-NEXT: 1 1 0.17 1 AscalonFX SUB sub s2, a2, a3 +# CHECK-NEXT: 1 7 7.00 7 AscalonFX[7],AscalonFXA[7] DIV div t1, t2, t3 +# CHECK-NEXT: 1 1 0.17 1 AscalonFX ADD add t1, a4, gp +# CHECK-NEXT: 1 7 7.00 7 AscalonFX[7],AscalonFXA[7] DIV div a1, a2, a3 +# CHECK-NEXT: 1 1 0.17 1 AscalonFX ADD add t1, a0, t0 +# CHECK-NEXT: 1 3 1.00 3 AscalonFX,AscalonFXA C_MUL mul s0, s0, a5 +# CHECK-NEXT: 1 1 0.17 1 AscalonFX C_ADD add t2, t2, t2 +# CHECK-NEXT: 1 1 0.17 1 AscalonFX SUB sub s1, s0, s1 +# CHECK-NEXT: 1 1 1.00 1 AscalonFX,AscalonFXB FCVT_S_W fcvt.s.w ft1, t3 +# CHECK-NEXT: 1 1 0.17 1 AscalonFX C_ADD add s2, s2, s2 +# CHECK-NEXT: 1 1 1.00 1 AscalonFX,AscalonFXA FCVT_W_S fcvt.w.s t5, ft3 # CHECK: Resources: # CHECK-NEXT: [0] - AscalonFPA @@ -63,19 +70,19 @@ fcvt.w.s t5, f3 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] -# CHECK-NEXT: - - 17.00 1.00 2.00 2.00 1.00 1.00 - - - - - +# CHECK-NEXT: - - 18.00 2.00 1.00 1.00 1.00 1.00 - - - - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions: # CHECK-NEXT: - - 1.00 - - - - - - - - - - mul t0, a0, t0 -# CHECK-NEXT: - - - - - - - 1.00 - - - - - sub s2, a2, a3 +# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - sub s2, a2, a3 # CHECK-NEXT: - - 7.00 - - - - - - - - - - div t1, t2, t3 -# CHECK-NEXT: - - - - - - 1.00 - - - - - - add t1, a4, gp +# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - add t1, a4, gp # CHECK-NEXT: - - 7.00 - - - - - - - - - - div a1, a2, a3 -# CHECK-NEXT: - - - - - 1.00 - - - - - - - add t1, a0, t0 +# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - add t1, a0, t0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - mul s0, s0, a5 -# CHECK-NEXT: - - - - - 1.00 - - - - - - - add t2, t2, t2 -# CHECK-NEXT: - - - - 1.00 - - - - - - - - sub s1, s0, s1 +# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - add t2, t2, t2 +# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - sub s1, s0, s1 # CHECK-NEXT: - - - 1.00 - - - - - - - - - fcvt.s.w ft1, t3 -# CHECK-NEXT: - - - - 1.00 - - - - - - - - add s2, s2, s2 +# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - add s2, s2, s2 # CHECK-NEXT: - - 1.00 - - - - - - - - - - fcvt.w.s t5, ft3 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vdiv_vsqrt.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vdiv_vsqrt.s index 53468935969e85..78543ff2f9dd7c 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vdiv_vsqrt.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vdiv_vsqrt.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e8, mf8, tu, mu vdiv.vv v8, v16, v24 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vislide-vx.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vislide-vx.s index b8ac1beea93bd7..a3fefc4fd6c1f5 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vislide-vx.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vislide-vx.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e32, m2, tu, mu vslidedown.vx v5, v7, x6 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vle-vse-vlm.s index 291c810b423e2f..d90a5ce1f2d73c 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vle-vse-vlm.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vle-vse-vlm.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e8, mf8, ta, ma vle8.v v8, (a0) diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlse-vsse.s index 4b9840eb77d448..75fccdaa687384 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlse-vsse.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlse-vsse.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e8, mf8, ta, ma vlse8.v v8, (a0), t0 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlseg-vsseg.s index 8871d645824399..dfec8437ae84ab 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlseg-vsseg.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlseg-vsseg.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e8, mf8, tu, mu vlseg2e8.v v8,(a0) diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlxe-vsxe.s index cc8dac76bf59c6..c0aad4ee904907 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlxe-vsxe.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlxe-vsxe.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e8, mf8, ta, ma vluxei8.v v8, (a0), v0 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vmv.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vmv.s index 45838b902a9d6e..05d457c1514fb4 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vmv.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vmv.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e8, mf8, tu, mu vmv1r.v v8, v16 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vreduce.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vreduce.s index 5a8b27eefaa3f4..c8c3340e4473e7 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vreduce.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vreduce.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s # Simple integer reductions: varies by LMUL vsetvli zero, zero, e32, m1, tu, mu diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vrgather-vcompress.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vrgather-vcompress.s index 0924322ac19f86..6d8d63bccfe3a4 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vrgather-vcompress.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vrgather-vcompress.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e32, m1, tu, mu vrgather.vv v5, v7, v8 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vshift-vmul.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vshift-vmul.s index 351d0653c0807a..805f5c00a231a0 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vshift-vmul.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vshift-vmul.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x --instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e32, m1, ta, ma _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
