https://github.com/dobri01 updated https://github.com/llvm/llvm-project/pull/229055
>From 143bf25c1925f5e57f32786f8f0b991f13e953f7 Mon Sep 17 00:00:00 2001 From: Alex Dobrescu <[email protected]> Date: Wed, 23 Sep 2026 14:19:33 +0100 Subject: [PATCH] [AArch64] Add support for C2 CPUs Add initial Armv9.3-A support for Arm C2-Pro and C2-Ultra. C2-Pro is another name for C1-Pro and uses a processor alias. C2-Ultra has its own architectural feature list, tuning family and host CPU part 0xd96. Its initial features and tuning follow C1-Ultra, and it reuses the C1-Ultra scheduling model pending a dedicated model. For more information see: https://developer.arm.com/Processors/C2-Ultra https://developer.arm.com/Processors/C1-Pro C2-Ultra Technical Reference Manual: https://developer.arm.com/documentation/109736/latest C1-Pro Technical Reference Manual (also applies to C2-Pro): https://developer.arm.com/documentation/107771/latest Signed-off-by: Alex Dobrescu <[email protected]> --- clang/docs/ReleaseNotes.md | 6 ++ clang/test/Driver/aarch64-mcpu.c | 4 ++ clang/test/Driver/aarch64-mtune.c | 6 ++ .../print-enabled-extensions/aarch64-c2-pro.c | 70 +++++++++++++++++++ .../aarch64-c2-ultra.c | 70 +++++++++++++++++++ .../Misc/target-invalid-cpu-note/aarch64.c | 2 + llvm/docs/ReleaseNotes.md | 2 + llvm/lib/Target/AArch64/AArch64Processors.td | 31 ++++++++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 1 + llvm/lib/TargetParser/Host.cpp | 1 + llvm/unittests/TargetParser/Host.cpp | 6 ++ .../TargetParser/TargetParserTest.cpp | 5 +- 12 files changed, 203 insertions(+), 1 deletion(-) create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c2-pro.c create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c2-ultra.c diff --git a/clang/docs/ReleaseNotes.md b/clang/docs/ReleaseNotes.md index cb3657952dbe88..d3471393d9e9d4 100644 --- a/clang/docs/ReleaseNotes.md +++ b/clang/docs/ReleaseNotes.md @@ -924,6 +924,12 @@ features cannot lower the translation-unit ABI level; #### Arm and AArch64 Support +- Added support for the following Arm processors (command-line identifiers in + parentheses): + + - C2-Pro (`c2-pro`), an alias for C1-Pro. + - C2-Ultra (`c2-ultra`). + - Added support for pointer authentication discrimination of C++ virtual table pointers stored in VTTs via the `-fptrauth-vtt-vtable-pointer-discrimination` option. diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c index 4dbc3480464d33..1a19469e5775de 100644 --- a/clang/test/Driver/aarch64-mcpu.c +++ b/clang/test/Driver/aarch64-mcpu.c @@ -94,6 +94,10 @@ // C1-PREMIUM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-premium" // RUN: %clang --target=aarch64 -mcpu=c1-ultra -### -c %s 2>&1 | FileCheck -check-prefix=C1-ULTRA %s // C1-ULTRA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-ultra" +// RUN: %clang --target=aarch64 -mcpu=c2-pro -### -c %s 2>&1 | FileCheck -check-prefix=C2-PRO %s +// C2-PRO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-pro" +// RUN: %clang --target=aarch64 -mcpu=c2-ultra -### -c %s 2>&1 | FileCheck -check-prefix=C2-ULTRA %s +// C2-ULTRA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c2-ultra" // RUN: %clang --target=aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXR82 %s // CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82" diff --git a/clang/test/Driver/aarch64-mtune.c b/clang/test/Driver/aarch64-mtune.c index 2518214f56750c..44921177be7692 100644 --- a/clang/test/Driver/aarch64-mtune.c +++ b/clang/test/Driver/aarch64-mtune.c @@ -12,6 +12,12 @@ // RUN: %clang -### -c --target=aarch64 %s -mtune=neoverse-n1 2>&1 | FileCheck %s --check-prefixes=GENERIC-CPU,NEOVERSE-N1 // NEOVERSE-N1: "-tune-cpu" "neoverse-n1" +// RUN: %clang -### -c --target=aarch64 %s -mtune=c2-pro 2>&1 | FileCheck %s --check-prefixes=GENERIC-CPU,C2-PRO +// C2-PRO: "-tune-cpu" "c2-pro" + +// RUN: %clang -### -c --target=aarch64 %s -mtune=c2-ultra 2>&1 | FileCheck %s --check-prefixes=GENERIC-CPU,C2-ULTRA +// C2-ULTRA: "-tune-cpu" "c2-ultra" + // RUN: %clang -### -c --target=aarch64 %s -mtune=thunderx2t99 2>&1 | FileCheck %s -check-prefixes=GENERIC-CPU,THUNDERX2T99 // THUNDERX2T99: "-tune-cpu" "thunderx2t99" diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c2-pro.c b/clang/test/Driver/print-enabled-extensions/aarch64-c2-pro.c new file mode 100644 index 00000000000000..f7a40fe93acb57 --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/aarch64-c2-pro.c @@ -0,0 +1,70 @@ +// REQUIRES: aarch64-registered-target +// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c2-pro | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s + +// CHECK: Extensions enabled for the given AArch64 target +// CHECK-EMPTY: +// CHECK-NEXT: Architecture Feature(s) Description +// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension +// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support +// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions +// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension +// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification +// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets +// CHECK-NEXT: FEAT_CHK Enable Armv8.0-A Check Feature Status Extension +// CHECK-NEXT: FEAT_CLRBHB Enable Clear BHB instruction +// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions +// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction +// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions +// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence +// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence +// CHECK-NEXT: FEAT_DotProd Enable dot product support +// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension +// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension +// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support +// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension +// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions +// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions +// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing +// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement +// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int +// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions +// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons +// CHECK-NEXT: FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension +// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension +// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions +// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension +// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension +// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets +// CHECK-NEXT: FEAT_LRCPC3 Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set +// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions +// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules +// CHECK-NEXT: FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions +// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension +// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension +// CHECK-NEXT: FEAT_NMI, FEAT_GICv3_NMI Enable Armv8.8-A Non-maskable Interrupts +// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement +// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension +// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants +// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension +// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension +// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions +// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions +// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier +// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension +// CHECK-NEXT: FEAT_SME Enable Scalable Matrix Extension (SME) +// CHECK-NEXT: FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions +// CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension +// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions +// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction +// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension +// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit +// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions +// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions +// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions +// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions +// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension +// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension +// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState +// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension +// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction +// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c2-ultra.c b/clang/test/Driver/print-enabled-extensions/aarch64-c2-ultra.c new file mode 100644 index 00000000000000..eb755ed9a37a50 --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/aarch64-c2-ultra.c @@ -0,0 +1,70 @@ +// REQUIRES: aarch64-registered-target +// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c2-ultra | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s + +// CHECK: Extensions enabled for the given AArch64 target +// CHECK-EMPTY: +// CHECK-NEXT: Architecture Feature(s) Description +// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension +// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support +// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions +// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension +// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification +// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets +// CHECK-NEXT: FEAT_CHK Enable Armv8.0-A Check Feature Status Extension +// CHECK-NEXT: FEAT_CLRBHB Enable Clear BHB instruction +// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions +// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction +// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions +// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence +// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence +// CHECK-NEXT: FEAT_DotProd Enable dot product support +// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension +// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension +// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support +// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension +// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions +// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions +// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing +// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement +// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int +// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions +// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons +// CHECK-NEXT: FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension +// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension +// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions +// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension +// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension +// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets +// CHECK-NEXT: FEAT_LRCPC3 Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set +// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions +// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules +// CHECK-NEXT: FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions +// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension +// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension +// CHECK-NEXT: FEAT_NMI, FEAT_GICv3_NMI Enable Armv8.8-A Non-maskable Interrupts +// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement +// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension +// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants +// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension +// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension +// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions +// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions +// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier +// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension +// CHECK-NEXT: FEAT_SME Enable Scalable Matrix Extension (SME) +// CHECK-NEXT: FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions +// CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension +// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions +// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction +// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension +// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit +// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions +// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions +// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions +// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions +// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension +// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension +// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState +// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension +// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction +// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction diff --git a/clang/test/Misc/target-invalid-cpu-note/aarch64.c b/clang/test/Misc/target-invalid-cpu-note/aarch64.c index 74b06db2d4f2f5..40de93a2bb1be1 100644 --- a/clang/test/Misc/target-invalid-cpu-note/aarch64.c +++ b/clang/test/Misc/target-invalid-cpu-note/aarch64.c @@ -42,6 +42,8 @@ // CHECK-SAME: {{^}}, c1-premium // CHECK-SAME: {{^}}, c1-pro // CHECK-SAME: {{^}}, c1-ultra +// CHECK-SAME: {{^}}, c2-pro +// CHECK-SAME: {{^}}, c2-ultra // CHECK-SAME: {{^}}, carmel // CHECK-SAME: {{^}}, cobalt-100 // CHECK-SAME: {{^}}, cortex-a320 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 7c09b303442a37..3a46c20d0c920a 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -234,6 +234,8 @@ Makes programs 10x faster by doing Special New Thing. ### Changes to the AArch64 Backend +- Added support for C2-Pro and C2-Ultra CPUs. + ### Changes to the AMDGPU Backend * Replaced `xnack` and `sramecc` target features with `amdgpu.xnack` diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index c0bbcc8cd4537c..f8d08efad99a72 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -354,6 +354,20 @@ def TuneC1Ultra : SubtargetFeature<"c1-ultra", "ARMProcFamily", FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive]>; +def TuneC2Ultra : SubtargetFeature<"c2-ultra", "ARMProcFamily", + "C2Ultra", "C2-Ultra ARM Processors",[ + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeatureFuseCmpCSel, + FeatureFuseCmpCSet, + FeatureFuseAES, + FeaturePostRAScheduler, + FeatureEnableSelectOptimize, + FeatureUseFixedOverScalableIfEqualCost, + FeatureMaxInterleaveFactor4, + FeatureAvoidLDAPUR, + FeaturePredictableSelectIsExpensive]>; + def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", "Fujitsu A64FX processors", [ FeaturePostRAScheduler, @@ -1016,6 +1030,20 @@ def ProcessorFeatures { FeatureSPE_EEF, FeatureRCPC3, FeatureETE, FeatureSVEBitPerm, FeatureSVE2, FeatureTRBE, FeatureSME, FeatureSME2]; + list<SubtargetFeature> C2Ultra = [HasV9_3aOps, FeatureNEON, FeatureCLRBHB, + FeatureCHK, FeatureFPARMv8, FeaturePerfMon, + FeatureSPECRES2, FeatureSSBS, FeatureRDM, + FeatureVH, FeatureBF16, FeatureDotProd, + FeatureFP16FML, FeatureFullFP16, + FeatureMPAM, FeatureSPE, FeatureSVE, + FeatureCCIDX, FeatureComplxNum, FeatureFPAC, + FeatureJS, FeatureAM, FeatureRAS, + FeatureSEL2, FeatureTRACEV8_4, + FeatureAltFPCmp, FeatureFRInt3264, + FeatureMTE, FeatureFineGrainedTraps, + FeatureSPE_EEF, FeatureRCPC3, + FeatureETE, FeatureSVEBitPerm, FeatureSVE2, + FeatureTRBE, FeatureSME, FeatureSME2]; list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, FeatureSHA2, FeaturePerfMon, FeatureFullFP16, FeatureSVE, FeatureComplxNum, @@ -1348,6 +1376,7 @@ def : ProcessorModel<"cortex-a725", NeoverseN3Model, ProcessorFeatures.A725, [TuneA725]>; def : ProcessorModel<"c1-pro", NeoverseN3Model, ProcessorFeatures.C1Pro, [TuneC1Pro]>; +def : ProcessorAlias<"c2-pro", "c1-pro">; def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, [TuneR82]>; def : ProcessorModel<"cortex-r82ae", CortexA55Model, ProcessorFeatures.R82AE, @@ -1368,6 +1397,8 @@ def : ProcessorModel<"c1-premium", C1PremiumModel, ProcessorFeatures.C1Premium, [TuneC1Premium]>; def : ProcessorModel<"c1-ultra", C1UltraModel, ProcessorFeatures.C1Ultra, [TuneC1Ultra]>; +def : ProcessorModel<"c2-ultra", C1UltraModel, + ProcessorFeatures.C2Ultra, [TuneC2Ultra]>; def : ProcessorModel<"gb10", NeoverseV3Model, ProcessorFeatures.GB10, [TuneX925]>; def : ProcessorModel<"grace", NeoverseV2Model, ProcessorFeatures.Grace, diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index 4fef12ab37ad86..c2c70c69d23c36 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -192,6 +192,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) { case CortexX925: case C1Premium: case C1Ultra: + case C2Ultra: PrefFunctionAlignment = Align(16); VScaleForTuning = 1; PrefLoopAlignment = Align(32); diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index 56f2757d3fd3a3..5bc4f2a8a9d2e7 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -207,6 +207,7 @@ getHostCPUNameForARMFromComponents(StringRef Implementer, StringRef Hardware, .Case("0xd90", "c1-premium") .Case("0xd8b", "c1-pro") .Case("0xd8c", "c1-ultra") + .Case("0xd96", "c2-ultra") .Case("0xc05", "cortex-a5") .Case("0xc07", "cortex-a7") .Case("0xc08", "cortex-a8") diff --git a/llvm/unittests/TargetParser/Host.cpp b/llvm/unittests/TargetParser/Host.cpp index 62f2278cea66b1..05bc220cfb5cda 100644 --- a/llvm/unittests/TargetParser/Host.cpp +++ b/llvm/unittests/TargetParser/Host.cpp @@ -160,6 +160,12 @@ TEST(getLinuxHostCPUName, AArch64) { EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n" "CPU part : 0xd8c"), "c1-ultra"); + EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n" + "CPU part : 0xd96"), + "c2-ultra"); + EXPECT_EQ(sys::detail::getHostCPUNameForARM( + 0x410fd961, ArrayRef<uint64_t>{0x410fd961}), + "c2-ultra"); EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n" "CPU part : 0xc00"), "falkor"); diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 78a13daac28678..6162c2da7a55b1 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1160,6 +1160,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64CPUTestParams("c1-premium", "armv9.3-a"), AArch64CPUTestParams("c1-pro", "armv9.3-a"), AArch64CPUTestParams("c1-ultra", "armv9.3-a"), + AArch64CPUTestParams("c2-pro", "armv9.3-a"), + AArch64CPUTestParams("c2-ultra", "armv9.3-a"), AArch64CPUTestParams("cyclone", "armv8-a"), AArch64CPUTestParams("apple-a7", "armv8-a"), AArch64CPUTestParams("apple-a8", "armv8-a"), @@ -1294,6 +1296,7 @@ TEST_P(AArch64CPUAliasTestFixture, testCPUAlias) { INSTANTIATE_TEST_SUITE_P( AArch64CPUAliasTests, AArch64CPUAliasTestFixture, ::testing::Values(AArch64CPUAliasTestParams({"neoverse-n2", "cobalt-100"}), + AArch64CPUAliasTestParams({"c1-pro", "c2-pro"}), AArch64CPUAliasTestParams({"apple-a7", "cyclone", "apple-a8", "apple-a9"}), AArch64CPUAliasTestParams({"apple-a12", "apple-s4", @@ -1309,7 +1312,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64CPUAliasTestParams::PrintToStringParamName); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 101; +static constexpr unsigned NumAArch64CPUArchs = 103; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector<StringRef, NumAArch64CPUArchs> List; _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
