llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clangir Author: Andrzej Warzyński (banach-space) <details> <summary>Changes</summary> Adds missing code-gen tests for DUP intrinsics operating on bf16. --- Full diff: https://github.com/llvm/llvm-project/pull/223799.diff 3 Files Affected: - (modified) clang/lib/CIR/CodeGen/CIRGenBuilder.h (+1-1) - (modified) clang/lib/CIR/CodeGen/CIRGenTypes.cpp (+1-1) - (modified) clang/test/CodeGen/AArch64/sve/dup.c (+57) ``````````diff diff --git a/clang/lib/CIR/CodeGen/CIRGenBuilder.h b/clang/lib/CIR/CodeGen/CIRGenBuilder.h index a710d8e0bbb87..91e3b18a6b315 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuilder.h +++ b/clang/lib/CIR/CodeGen/CIRGenBuilder.h @@ -322,7 +322,7 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy { cir::IntType getUInt64Ty() { return typeCache.uInt64Ty; } cir::FP16Type getFp16Ty() { return typeCache.fP16Ty; } - cir::BF16Type getBfloat6Ty() { return typeCache.bFloat16Ty; } + cir::BF16Type getBfloat16Ty() { return typeCache.bFloat16Ty; } cir::SingleType getSingleTy() { return typeCache.floatTy; } cir::DoubleType getDoubleTy() { return typeCache.doubleTy; } diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp index f2cb875e908a7..dd91284bef3fe 100644 --- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp @@ -398,7 +398,7 @@ mlir::Type CIRGenTypes::convertType(QualType type) { /*is_scalable=*/true); break; case BuiltinType::SveBFloat16: - resultType = cir::VectorType::get(builder.getFp16Ty(), 8, + resultType = cir::VectorType::get(builder.getBfloat16Ty(), 8, /*is_scalable=*/true); break; case BuiltinType::SveInt32: diff --git a/clang/test/CodeGen/AArch64/sve/dup.c b/clang/test/CodeGen/AArch64/sve/dup.c index 80a7a888339ff..f31221578c5c7 100644 --- a/clang/test/CodeGen/AArch64/sve/dup.c +++ b/clang/test/CodeGen/AArch64/sve/dup.c @@ -209,6 +209,17 @@ svbool_t test_svdup_n_b64(bool op) MODE_ATTR return SVE_ACLE_FUNC(svdup,_n,_b64,)(op); } +// ALL-LABEL: @test_svdup_n_bf16( +svbfloat16_t test_svdup_n_bf16(bfloat16_t op) MODE_ATTR { +// CIR: cir.call_llvm_intrinsic "aarch64.sve.dup.x" %{{.*}} : (!cir.bf16) -> !cir.vector<[8] x !cir.bf16> + +// LLVM: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x bfloat> poison, bfloat [[OP:%.*]], i64 0 +// LLVM: [[TMP0:%.*]] = shufflevector <vscale x 8 x bfloat> [[DOTSPLATINSERT]], <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer +// LLVM: ret <vscale x 8 x bfloat> [[TMP0]] + // expected-warning@+1 {{implicit declaration of function 'svdup_n_bf16'}} + return SVE_ACLE_FUNC(svdup, _n, _bf16, )(op); +} + //===------------------------------------------------------===// // 2. PREDICATED ZERO-ING SVDUP //===------------------------------------------------------===// @@ -383,6 +394,17 @@ svfloat64_t test_svdup_n_f64_z(svbool_t pg, float64_t op) MODE_ATTR return SVE_ACLE_FUNC(svdup,_n,_f64_z,)(pg, op); } +// ALL-LABEL: @test_svdup_n_bf16_z( +svbfloat16_t test_svdup_n_bf16_z(svbool_t pg, bfloat16_t op) MODE_ATTR { +// CIR: cir.call_llvm_intrinsic "aarch64.sve.dup" %{{.*}} %{{.*}} %{{.*}} : (!cir.vector<[8] x !cir.bf16>, !cir.vector<[8] x !cir.int<u, 1>>, !cir.bf16) -> !cir.vector<[8] x !cir.bf16> + +// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// LLVM: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.nxv8bf16(<vscale x 8 x bfloat> zeroinitializer, <vscale x 8 x i1> [[TMP0]], bfloat [[OP:%.*]]) +// LLVM: ret <vscale x 8 x bfloat> [[TMP1]] + // expected-warning@+1 {{implicit declaration of function 'svdup_n_bf16_z'}} + return SVE_ACLE_FUNC(svdup, _n, _bf16_z, )(pg, op); +} + //===------------------------------------------------------===// // 3. PREDICATED MERGING-ING SVDUP (Op1) //===------------------------------------------------------===// @@ -544,6 +566,17 @@ svfloat64_t test_svdup_n_f64_m(svfloat64_t inactive, svbool_t pg, float64_t op) return SVE_ACLE_FUNC(svdup,_n,_f64_m,)(inactive, pg, op); } +// ALL-LABEL: @test_svdup_n_bf16_m( +svbfloat16_t test_svdup_n_bf16_m(svbfloat16_t inactive, svbool_t pg, bfloat16_t op) MODE_ATTR { +// CIR: cir.call_llvm_intrinsic "aarch64.sve.dup" %{{.*}} %{{.*}} %{{.*}} : (!cir.vector<[8] x !cir.bf16>, !cir.vector<[8] x !cir.int<u, 1>>, !cir.bf16) -> !cir.vector<[8] x !cir.bf16> + +// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// LLVM: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.nxv8bf16(<vscale x 8 x bfloat> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], bfloat [[OP:%.*]]) +// LLVM: ret <vscale x 8 x bfloat> [[TMP1]] + // expected-warning@+1 {{implicit declaration of function 'svdup_n_bf16_m'}} + return SVE_ACLE_FUNC(svdup, _n, _bf16_m, )(inactive, pg, op); +} + //===------------------------------------------------------===// // 4. PREDICATED MERGING-ING SVDUP (MergeAnyExp) //===------------------------------------------------------===// @@ -718,6 +751,17 @@ svfloat64_t test_svdup_n_f64_x(svbool_t pg, float64_t op) MODE_ATTR return SVE_ACLE_FUNC(svdup,_n,_f64_x,)(pg, op); } +// ALL-LABEL: @test_svdup_n_bf16_x( +svbfloat16_t test_svdup_n_bf16_x(svbool_t pg, bfloat16_t op) MODE_ATTR { +// CIR: cir.call_llvm_intrinsic "aarch64.sve.dup" %{{.*}} %{{.*}} %{{.*}} : (!cir.vector<[8] x !cir.bf16>, !cir.vector<[8] x !cir.int<u, 1>>, !cir.bf16) -> !cir.vector<[8] x !cir.bf16> + +// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// LLVM: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.nxv8bf16(<vscale x 8 x bfloat> undef, <vscale x 8 x i1> [[TMP0]], bfloat [[OP:%.*]]) +// LLVM: ret <vscale x 8 x bfloat> [[TMP1]] + // expected-warning@+1 {{implicit declaration of function 'svdup_n_bf16_x'}} + return SVE_ACLE_FUNC(svdup, _n, _bf16_x, )(pg, op); +} + //===------------------------------------------------------===// // 5. SVDUP_LANE //===------------------------------------------------------===// @@ -874,3 +918,16 @@ svfloat64_t test_svdup_lane_f64(svfloat64_t data, uint64_t index) MODE_ATTR // LLVM: ret <vscale x 2 x double> [[TMP0]] return SVE_ACLE_FUNC(svdup_lane,_f64,,)(data, index); } + +// ALL-LABEL: @test_svdup_lane_bf16( +svbfloat16_t test_svdup_lane_bf16(svbfloat16_t data, uint16_t index) MODE_ATTR +{ +// CIR: cir.call_llvm_intrinsic "aarch64.sve.tbl" %{{.*}} %{{.*}} : (!cir.vector<[8] x !cir.bf16>, !cir.vector<[8] x !u16i>) -> !cir.vector<[8] x !cir.bf16> + +// LLVM: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[INDEX:%.*]], i64 0 +// LLVM: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer +// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat> [[DATA:%.*]], <vscale x 8 x i16> [[DOTSPLAT]]) +// LLVM: ret <vscale x 8 x bfloat> [[TMP0]] + // expected-warning@+1 {{implicit declaration of function 'svdup_lane_bf16'}} + return SVE_ACLE_FUNC(svdup_lane,_bf16,,)(data, index); +} `````````` </details> https://github.com/llvm/llvm-project/pull/223799 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
