llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: 陈子昂 (Michael-Chen-NJU) <details> <summary>Changes</summary> Add packed widening add/sub header wrappers for the RISC-V P extension using generic vector IR. --- Patch is 28.55 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/219348.diff 6 Files Affected: - (modified) clang/lib/Headers/riscv_packed_simd.h (+17) - (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+208) - (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+74) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+71) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+35) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+151-5) ``````````diff diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index 946dd936d49cd..a3f72211d0feb 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -142,6 +142,12 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8))); static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \ return __builtin_convertvector(__rs1, rty); \ } +#define __packed_widen_binary_op(name, rty, ty, op) \ + static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \ + ty __rs2) { \ + return __builtin_convertvector(__rs1, rty) \ + op __builtin_convertvector(__rs2, rty); \ + } #define __packed_widen_mul(name, rty, ty) \ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \ ty __rs2) { \ @@ -604,6 +610,16 @@ __packed_widen_high4(pwcvth_u16x4, uint16x4_t, uint8x4_t) __packed_widen_high2(pwcvth_i32x2, int32x2_t, int16x2_t) __packed_widen_high2(pwcvth_u32x2, uint32x2_t, uint16x2_t) +/* Packed Widening Addition and Subtraction */ +__packed_widen_binary_op(pwadd_i16x4, int16x4_t, int8x4_t, +) +__packed_widen_binary_op(pwadd_i32x2, int32x2_t, int16x2_t, +) +__packed_widen_binary_op(pwaddu_u16x4, uint16x4_t, uint8x4_t, +) +__packed_widen_binary_op(pwaddu_u32x2, uint32x2_t, uint16x2_t, +) +__packed_widen_binary_op(pwsub_i16x4, int16x4_t, int8x4_t, -) +__packed_widen_binary_op(pwsub_i32x2, int32x2_t, int16x2_t, -) +__packed_widen_binary_op(pwsubu_u16x4, uint16x4_t, uint8x4_t, -) +__packed_widen_binary_op(pwsubu_u32x2, uint32x2_t, uint16x2_t, -) + /* Packed Widening Multiply (32-bit) */ __packed_widen_mul(pwmul_i16x4, int16x4_t, int8x4_t) __packed_widen_mul(pwmul_i32x2, int32x2_t, int16x2_t) @@ -1004,6 +1020,7 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t) #undef __packed_merge_builtin #undef __packed_unary_builtin #undef __packed_widen_convert +#undef __packed_widen_binary_op #undef __packed_widen_mul #undef __packed_widen_mulsu #undef __packed_widen_high2 diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 74a7cb60a6afa..af45d4235b068 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -8032,6 +8032,214 @@ uint32x2_t test_pwcvtu_u32x2(uint16x2_t rs1) { return __riscv_pwcvtu_u32x2(rs1); } +// RV32-LABEL: define dso_local i64 @test_pwadd_i16x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16> +// RV32-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16> +// RV32-NEXT: [[ADD_I:%.*]] = add nsw <4 x i16> [[CONV_I]], [[CONV3_I]] +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pwadd_i16x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16> +// RV64-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16> +// RV64-NEXT: [[ADD_I:%.*]] = add nsw <4 x i16> [[CONV_I]], [[CONV3_I]] +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int16x4_t test_pwadd_i16x4(int8x4_t rs1, int8x4_t rs2) { + return __riscv_pwadd_i16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pwadd_i32x2( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32> +// RV32-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32> +// RV32-NEXT: [[ADD_I:%.*]] = add nsw <2 x i32> [[CONV_I]], [[CONV3_I]] +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pwadd_i32x2( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32> +// RV64-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32> +// RV64-NEXT: [[ADD_I:%.*]] = add nsw <2 x i32> [[CONV_I]], [[CONV3_I]] +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int32x2_t test_pwadd_i32x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pwadd_i32x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pwaddu_u16x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16> +// RV32-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16> +// RV32-NEXT: [[ADD_I:%.*]] = add nuw nsw <4 x i16> [[CONV_I]], [[CONV3_I]] +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pwaddu_u16x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16> +// RV64-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16> +// RV64-NEXT: [[ADD_I:%.*]] = add nuw nsw <4 x i16> [[CONV_I]], [[CONV3_I]] +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +uint16x4_t test_pwaddu_u16x4(uint8x4_t rs1, uint8x4_t rs2) { + return __riscv_pwaddu_u16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pwaddu_u32x2( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32> +// RV32-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32> +// RV32-NEXT: [[ADD_I:%.*]] = add nuw nsw <2 x i32> [[CONV_I]], [[CONV3_I]] +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pwaddu_u32x2( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32> +// RV64-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32> +// RV64-NEXT: [[ADD_I:%.*]] = add nuw nsw <2 x i32> [[CONV_I]], [[CONV3_I]] +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +uint32x2_t test_pwaddu_u32x2(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pwaddu_u32x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pwsub_i16x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16> +// RV32-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16> +// RV32-NEXT: [[SUB_I:%.*]] = sub nsw <4 x i16> [[CONV_I]], [[CONV3_I]] +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pwsub_i16x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16> +// RV64-NEXT: [[CONV3_I:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i16> +// RV64-NEXT: [[SUB_I:%.*]] = sub nsw <4 x i16> [[CONV_I]], [[CONV3_I]] +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int16x4_t test_pwsub_i16x4(int8x4_t rs1, int8x4_t rs2) { + return __riscv_pwsub_i16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pwsub_i32x2( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32> +// RV32-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32> +// RV32-NEXT: [[SUB_I:%.*]] = sub nsw <2 x i32> [[CONV_I]], [[CONV3_I]] +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pwsub_i32x2( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32> +// RV64-NEXT: [[CONV3_I:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32> +// RV64-NEXT: [[SUB_I:%.*]] = sub nsw <2 x i32> [[CONV_I]], [[CONV3_I]] +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int32x2_t test_pwsub_i32x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pwsub_i32x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pwsubu_u16x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16> +// RV32-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16> +// RV32-NEXT: [[SUB_I:%.*]] = sub nsw <4 x i16> [[CONV_I]], [[CONV3_I]] +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pwsubu_u16x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16> +// RV64-NEXT: [[CONV3_I:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i16> +// RV64-NEXT: [[SUB_I:%.*]] = sub nsw <4 x i16> [[CONV_I]], [[CONV3_I]] +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +uint16x4_t test_pwsubu_u16x4(uint8x4_t rs1, uint8x4_t rs2) { + return __riscv_pwsubu_u16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pwsubu_u32x2( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32> +// RV32-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32> +// RV32-NEXT: [[SUB_I:%.*]] = sub nsw <2 x i32> [[CONV_I]], [[CONV3_I]] +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pwsubu_u32x2( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32> +// RV64-NEXT: [[CONV3_I:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32> +// RV64-NEXT: [[SUB_I:%.*]] = sub nsw <2 x i32> [[CONV_I]], [[CONV3_I]] +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +uint32x2_t test_pwsubu_u32x2(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pwsubu_u32x2(rs1, rs2); +} + // RV32-LABEL: define dso_local i64 @test_pwmul_i16x4( // RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { // RV32-NEXT: [[ENTRY:.*:]] diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 28e3a8911739d..4730f860cb6bf 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -2269,6 +2269,80 @@ uint32x2_t test_pwcvtu_u32x2(uint16x2_t rs1) { return __riscv_pwcvtu_u32x2(rs1); } +// CHECK-LABEL: test_pwadd_i16x4: +// RV32: pwadd.b +// RV64: zip8p +// RV64: psrai.h +// RV64: psext.h.b +// RV64: padd.h +int16x4_t test_pwadd_i16x4(int8x4_t rs1, int8x4_t rs2) { + return __riscv_pwadd_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pwadd_i32x2: +// RV32: pwadd.h +// RV64: zip16p +// RV64: pli.h +// RV64: pm2add.h +int32x2_t test_pwadd_i32x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pwadd_i32x2(rs1, rs2); +} + +// CHECK-LABEL: test_pwaddu_u16x4: +// RV32: pwaddu.b +// RV64: pwcvtu.wb +// RV64: pwcvtu.wb +// RV64: padd.h +uint16x4_t test_pwaddu_u16x4(uint8x4_t rs1, uint8x4_t rs2) { + return __riscv_pwaddu_u16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pwaddu_u32x2: +// RV32: pwaddu.h +// RV64: zip16p +// RV64: pli.h +// RV64: pm2addu.h +uint32x2_t test_pwaddu_u32x2(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pwaddu_u32x2(rs1, rs2); +} + +// CHECK-LABEL: test_pwsub_i16x4: +// RV32: pwsub.b +// RV64: zip8p +// RV64: psrai.h +// RV64: psext.h.b +// RV64: psub.h +int16x4_t test_pwsub_i16x4(int8x4_t rs1, int8x4_t rs2) { + return __riscv_pwsub_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pwsub_i32x2: +// RV32: pwsub.h +// RV64: zip16p +// RV64: pli.h +// RV64: pm2sub.h +int32x2_t test_pwsub_i32x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pwsub_i32x2(rs1, rs2); +} + +// CHECK-LABEL: test_pwsubu_u16x4: +// RV32: pwsubu.b +// RV64: pwcvtu.wb +// RV64: pwcvtu.wb +// RV64: psub.h +uint16x4_t test_pwsubu_u16x4(uint8x4_t rs1, uint8x4_t rs2) { + return __riscv_pwsubu_u16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pwsubu_u32x2: +// RV32: pwsubu.h +// RV64: pwcvtu.wh +// RV64: pwcvtu.wh +// RV64: psub.w +uint32x2_t test_pwsubu_u32x2(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pwsubu_u32x2(rs1, rs2); +} + // CHECK-LABEL: test_pwcvth_i16x4: // RV32: pwcvth.b // RV64: pwcvth.wb diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 470599784314a..794ac85f1cd78 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -17975,6 +17975,73 @@ static SDValue combineAddMulh(SDNode *N, SelectionDAG &DAG, return DAG.getNode(RISCVISD::MULHSU, DL, VT, X, Mulh.getOperand(1)); } +static SDValue combinePExtWideningAddSub(SDNode *N, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + // Recognize the RV64 decompositions listed for the 32-bit packed widening + // add/sub operations. Mixed signed/unsigned PM2 forms are outside that group. + if (!Subtarget.hasStdExtP() || !Subtarget.is64Bit()) + return SDValue(); + + unsigned Opcode = N->getOpcode(); + if (Opcode != ISD::ADD && Opcode != ISD::SUB) + return SDValue(); + + EVT VT = N->getValueType(0); + if (VT != MVT::v4i16 && VT != MVT::v2i32) + return SDValue(); + + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + bool N0IsSExt = N0.getOpcode() == ISD::SIGN_EXTEND; + bool N0IsZExt = N0.getOpcode() == ISD::ZERO_EXTEND; + bool N1IsSExt = N1.getOpcode() == ISD::SIGN_EXTEND; + bool N1IsZExt = N1.getOpcode() == ISD::ZERO_EXTEND; + if (!(N0IsSExt || N0IsZExt) || !(N1IsSExt || N1IsZExt) || !N0.hasOneUse() || + !N1.hasOneUse()) + return SDValue(); + + SDValue A = N0.getOperand(0); + SDValue B = N1.getOperand(0); + MVT SrcVT = VT == MVT::v4i16 ? MVT::v4i8 : MVT::v2i16; + MVT LegalSrcVT = VT == MVT::v4i16 ? MVT::v8i8 : MVT::v4i16; + if (A.getValueType() != SrcVT || B.getValueType() != SrcVT) + return SDValue(); + + if (VT == MVT::v4i16 && (!N0IsSExt || !N1IsSExt)) + return SDValue(); + + bool IsPM2Halfword = + VT == MVT::v2i32 && + ((N0IsSExt && N1IsSExt) || (Opcode == ISD::ADD && N0IsZExt && N1IsZExt)); + if (VT == MVT::v2i32 && !IsPM2Halfword) + return SDValue(); + + SDLoc DL(N); + A = DAG.getNode(ISD::CONCAT_VECTORS, DL, LegalSrcVT, A, DAG.getUNDEF(SrcVT)); + B = DAG.getNode(ISD::CONCAT_VECTORS, DL, LegalSrcVT, B, DAG.getUNDEF(SrcVT)); + + SDValue Zip = DAG.getNode(RISCVISD::PZIP, DL, LegalSrcVT, A, B); + if (VT == MVT::v4i16) { + SDValue ZipAsVT = DAG.getBitcast(VT, Zip); + SDValue Low = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, ZipAsVT, + DAG.getValueType(MVT::v4i8)); + SDValue High = DAG.getNode(RISCVISD::PSRA, DL, VT, ZipAsVT, + DAG.getConstant(8, DL, MVT::i64)); + return DAG.getNode(Opcode, DL, VT, Low, High); + } + + SDValue Ones = DAG.getConstant(1, DL, LegalSrcVT); + if (N0IsSExt && N1IsSExt) { + unsigned Opc = Opcode == ISD::ADD ? RISCVISD::PM2ADD_H : RISCVISD::PM2SUB_H; + return DAG.getNode(Opc, DL, VT, Zip, Ones); + } + + if (Opcode == ISD::ADD && N0IsZExt && N1IsZExt) + return DAG.getNode(RISCVISD::PM2ADDU_H, DL, VT, Zip, Ones); + + return SDValue(); +} + static SDValue performADDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget) { @@ -17993,6 +18060,8 @@ static SDValue performADDCombine(SDNode *N, return V; if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget)) return V; + if (SDValue V = combinePExtWideningAddSub(N, DAG, Subtarget)) + return V; if (SDValue V = combineBinOpOfZExt(N, DAG)) return V; if (SDValue V = combineAddMulh(N, DAG, Subtarget)) @@ -18122,6 +18191,8 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, } } + if (SDValue V = combinePExtWideningAddSub(N, DAG, Subtarget)) + return V; if (SDValue V = combineBinOpOfZExt(N, DAG)) return V; if (SDV... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/219348 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
