https://github.com/Siya-05 created https://github.com/llvm/llvm-project/pull/214781
Related: #179278 This patch adds initial support for CUDA built-in texture types in CIR for device-side compilation. CUDA texture references are lowered to the NVPTX device-handle representation (`i64`), matching existing Clang CodeGen behavior. ## Changes - Add `getCUDADeviceBuiltinTextureDeviceType()` target hook to `TargetCIRGenInfo` - Implement NVPTX texture lowering in `NVPTXTargetCIRGenInfo` - Handle CUDA built-in texture types in `CIRGenTypes::convertType` - Add initial CUDA texture variable registration bookkeeping in `CIRGenNVCUDARuntime` - Add CIR CUDA test coverage for device-side texture lowering ## Notes - This patch implements initial device-side texture type lowering support - Full CUDA runtime texture registration remains unsupported - Texture registration metadata such as texture type and normalized mode is left for follow-up work - TBAA handling for surface/texture types is left for follow-up work >From a8de904147e7c554f54b84988152faa924bfec91 Mon Sep 17 00:00:00 2001 From: Sivapriya Venkateswarar <[email protected]> Date: Fri, 7 Aug 2026 19:53:10 +0400 Subject: [PATCH] [CIR][CUDA] Support built-in CUDA texture type --- clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp | 24 +++++++++++++++++++++-- clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 4 ++++ clang/lib/CIR/CodeGen/TargetInfo.h | 4 ++++ clang/lib/CIR/CodeGen/Targets/NVPTX.cpp | 7 +++++++ clang/test/CIR/CodeGenCUDA/texture.cu | 26 +++++++++++++++++++++++++ 5 files changed, 63 insertions(+), 2 deletions(-) create mode 100644 clang/test/CIR/CodeGenCUDA/texture.cu diff --git a/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp b/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp index 2288c8bf5a818..ab4baf336d379 100644 --- a/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp @@ -119,6 +119,24 @@ class CIRGenNVCUDARuntime : public CIRGenCUDARuntime { cir::CUDADeviceVarKind::Surface, }); } + + void registerDeviceTex(const VarDecl *vd, cir::GlobalOp &var, bool isExtern) { + auto &builder = cgm.getBuilder(); + + var->setAttr(cir::CUDAVarRegistrationInfoAttr::getMnemonic(), + cir::CUDAVarRegistrationInfoAttr::get( + builder.getContext(), + getDeviceSideName(cast<NamedDecl>(vd)), + cir::CUDADeviceVarKind::Texture, isExtern, + /*isConstant=*/false, + /*isManaged=*/false)); + + deviceVars.push_back({ + var, + vd, + cir::CUDADeviceVarKind::Texture, + }); + } }; } // namespace @@ -484,8 +502,10 @@ void CIRGenNVCUDARuntime::handleVarRegistration(const VarDecl *vd, registerDeviceSurf(vd, var, !vd->hasDefinition()); } else if (vd->getType()->isCUDADeviceBuiltinTextureType()) { - cgm.errorNYI(vd->getSourceRange(), - "handleVarRegistration: Texture registration"); + // Builtin textures and their template arguments are also registered + // with CUDA runtime. + if (!vd->hasExternalStorage()) + registerDeviceTex(vd, var, !vd->hasDefinition()); } } diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp index e5af4eec7720f..8650af216f5f2 100644 --- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp @@ -311,6 +311,10 @@ mlir::Type CIRGenTypes::convertType(QualType type) { cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType()) return ty; } else if (type->isCUDADeviceBuiltinTextureType()) { + if (mlir::Type ty = + cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinTextureDeviceType()) + return ty; + assert(!cir::MissingFeatures::cudaTextureType()); } } diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h b/clang/lib/CIR/CodeGen/TargetInfo.h index 308d472234f99..03de9f71907af 100644 --- a/clang/lib/CIR/CodeGen/TargetInfo.h +++ b/clang/lib/CIR/CodeGen/TargetInfo.h @@ -70,6 +70,10 @@ class TargetCIRGenInfo { return nullptr; } + virtual mlir::Type getCUDADeviceBuiltinTextureDeviceType() const { + return nullptr; + } + /// Determine whether a call to an unprototyped functions under /// the given calling convention should use the variadic /// convention or the non-variadic convention. diff --git a/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp b/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp index 83904d1f16855..5de0c2f1264a1 100644 --- a/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp +++ b/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp @@ -77,6 +77,13 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo { return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64, /*isSigned=*/true); } + + mlir::Type getCUDADeviceBuiltinTextureDeviceType() const override { + // On the device side, texture reference is represented as an object handle + // in 64-bit integer. + return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64, + /*isSigned=*/true); + } }; } // namespace diff --git a/clang/test/CIR/CodeGenCUDA/texture.cu b/clang/test/CIR/CodeGenCUDA/texture.cu new file mode 100644 index 0000000000000..0f78d9a2d8248 --- /dev/null +++ b/clang/test/CIR/CodeGenCUDA/texture.cu @@ -0,0 +1,26 @@ +// REQUIRES: x86-registered-target +// REQUIRES: nvptx-registered-target +// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=CIR-DEVICE %s +// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=LLVM-DEVICE %s +// RUN: %clang_cc1 -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=OGCG-DEVICE %s + +struct textureReference { + int desc; +}; + +enum ReadMode { + ElementType = 0, + NormalizedFloat = 1 +}; + +template <typename T, int dim = 1, ReadMode mode = ElementType> +struct __attribute__((device_builtin_texture_type)) texture + : public textureReference {}; + +texture<float, 2, NormalizedFloat> tex; + +// CIR-DEVICE: cir.global external target_address_space(1) @tex = #cir.undef : !s64i + +// CIR now matches OG CodeGen and emits undef for CUDA shadow variables. +// LLVM-DEVICE: @tex ={{.*}} addrspace(1) externally_initialized global i64 undef +// OGCG-DEVICE: @tex ={{.*}} addrspace(1) externally_initialized global i64 undef \ No newline at end of file _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
