================
@@ -0,0 +1,82 @@
+// RUN: not cir-opt %s -cir-call-conv-lowering=target=x86_64 2>&1 | FileCheck
%s
+
+!s8i = !cir.int<s, 8>
+!s32i = !cir.int<s, 32>
+!u8i = !cir.int<u, 8>
+!u32i = !cir.int<u, 32>
+!rec_U = !cir.union<"U" {!s32i, !u32i}>
+!rec_P = !cir.struct<"P" packed {!s8i, !s32i}>
+!rec_Ov = !cir.struct<"Ov" padded {!s32i, !cir.array<!u8i x 12>}>
+!rec_E = !cir.struct<"E" {!cir.array<!u8i x 1>}>
+!rec_FF = !cir.struct<"FF" {!cir.float, !cir.float}>
+!rec_RetFF = !cir.struct<"RetFF" {!cir.float, !cir.float}>
+
+module attributes {
+ dlti.dl_spec = #dlti.dl_spec<
+ #dlti.dl_entry<i32, dense<32>: vector<2xi64>>,
+ #dlti.dl_entry<i64, dense<64>: vector<2xi64>>,
+ #dlti.dl_entry<f32, dense<32>: vector<2xi64>>,
+ #dlti.dl_entry<f64, dense<64>: vector<2xi64>>>
+} {
+
+ // A union is rejected: its register coercion needs a widen fixup.
+ cir.func @take_union(%arg0: !rec_U) {
+ cir.return
+ }
+
+ // CHECK-DAG: not yet implemented for type '!cir.union<"U"
----------------
adams381 wrote:
You're right, they come out in source order. Switched them to ordered CHECK.
https://github.com/llvm/llvm-project/pull/210528
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