================
@@ -5327,14 +5327,23 @@ static SDValue getSingleShuffleSrc(MVT VT, SDValue V1,
SDValue V2) {
return SDValue();
}
-static bool isLegalVTForZvzipOperand(MVT VT, const RISCVSubtarget &Subtarget) {
+static bool
+isLegalVTForZvzipDeinterleavedOperand(MVT VT, const RISCVSubtarget &Subtarget)
{
MVT ContainerVT = VT;
if (VT.isFixedLengthVector())
ContainerVT = getContainerForFixedLengthVector(VT, Subtarget);
// Determine LMUL of the container vector.
return RISCVTargetLowering::getLMUL(ContainerVT) != RISCVVType::LMUL_8;
}
+static bool
+isLegalVTForZvzipInterleavedOperand(MVT VT, const RISCVSubtarget &Subtarget) {
+ MVT ContainerVT = VT;
+ if (VT.isFixedLengthVector())
+ ContainerVT = getContainerForFixedLengthVector(VT, Subtarget);
+ return RISCVTargetLowering::getLMUL(ContainerVT) != RISCVVType::LMUL_F8;
----------------
BoyaoWang430 wrote:
This only excludes MF8, but Zvzip also requires 2 * SEW <= LMUL * min(ELEN,
VLEN). On Zve32x, e32,m1 passes here and leads to an illegal e32,mf2 result.
https://github.com/llvm/llvm-project/pull/210603
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