https://github.com/E00N777 updated https://github.com/llvm/llvm-project/pull/207189
>From 4f38c338a3741724bf78ca5c3629c311fad98a82 Mon Sep 17 00:00:00 2001 From: E00N777 <[email protected]> Date: Thu, 2 Jul 2026 21:24:05 +0800 Subject: [PATCH 1/2] [CIR][AArch64] Lower NEON Saturating substract intrinsics --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 34 +- clang/test/CodeGen/AArch64/neon-intrinsics.c | 326 ---------------- clang/test/CodeGen/AArch64/neon/subtraction.c | 367 ++++++++++++++++++ 3 files changed, 399 insertions(+), 328 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 9a50acece4d2c..1b2db4a35021e 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -470,6 +470,14 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( case NEON::BI__builtin_neon_vpmaxnms_f32: case NEON::BI__builtin_neon_vpmaxnmqd_f64: case NEON::BI__builtin_neon_vmulxh_f16: + case NEON::BI__builtin_neon_vqsubs_s32: + case NEON::BI__builtin_neon_vqsubs_u32: + case NEON::BI__builtin_neon_vqsubd_s64: + case NEON::BI__builtin_neon_vqsubd_u64: + case NEON::BI__builtin_neon_vqsubb_s8: + case NEON::BI__builtin_neon_vqsubb_u8: + case NEON::BI__builtin_neon_vqsubh_s16: + case NEON::BI__builtin_neon_vqsubh_u16: break; } @@ -483,8 +491,28 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( auto [funcResTy, argTypes] = deriveNeonSISDIntrinsicOperandTypes( cgf, info.TypeModifier, arg0Ty, resultTy, ops); - return emitNeonCall(cgf.cgm, builder, std::move(argTypes), ops, llvmIntrName, - funcResTy, loc); + // Scalar operands feeding a vector `argType` (e.g. vqsubb_s8, which has no + // scalar overload) are splatted into lane 0 of a poison vector. + for (unsigned i = 0, e = ops.size(); i != e; ++i) { + auto vecArgTy = mlir::dyn_cast<cir::VectorType>(argTypes[i]); + if (vecArgTy && !mlir::isa<cir::VectorType>(ops[i].getType()) && + cgf.cgm.getDataLayout().getTypeSizeInBits(ops[i].getType()) != + cgf.cgm.getDataLayout().getTypeSizeInBits(vecArgTy)) { + mlir::Value poison = + builder.getConstant(loc, cir::PoisonAttr::get(vecArgTy)); + ops[i] = builder.createInsertElement(loc, poison, ops[i], /*idx=*/0); + } + } + + mlir::Value result = emitNeonCall(cgf.cgm, builder, std::move(argTypes), ops, + llvmIntrName, funcResTy, loc); + + // Recover a scalar result from a wider vector intrinsic result via lane 0. + if (auto resVecTy = mlir::dyn_cast<cir::VectorType>(result.getType()); + resVecTy && cgf.cgm.getDataLayout().getTypeSizeInBits(resultTy) < + cgf.cgm.getDataLayout().getTypeSizeInBits(resVecTy)) + return builder.createExtractElement(loc, result, /*idx=*/0); + return result; } //===----------------------------------------------------------------------===// @@ -1162,6 +1190,8 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vhsubq_v: case NEON::BI__builtin_neon_vrhadd_v: case NEON::BI__builtin_neon_vrhaddq_v: + case NEON::BI__builtin_neon_vqsub_v: + case NEON::BI__builtin_neon_vqsubq_v: case NEON::BI__builtin_neon_vshl_v: case NEON::BI__builtin_neon_vshlq_v: case NEON::BI__builtin_neon_vraddhn_v: diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 883897a18cbf6..2afa1f6119ca1 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -2559,240 +2559,6 @@ uint64x2_t test_vqaddq_u64(uint64x2_t a, uint64x2_t b) { return vqaddq_u64(a, b); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vqsub_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSUB_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i8> [[VQSUB_V_I]] -// -int8x8_t test_vqsub_s8(int8x8_t a, int8x8_t b) { - return vqsub_s8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqsub_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> [[VQSUB_V_I]], <4 x i16> [[VQSUB_V1_I]]) -// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <4 x i16> [[VQSUB_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <4 x i16> -// CHECK-NEXT: ret <4 x i16> [[TMP2]] -// -int16x4_t test_vqsub_s16(int16x4_t a, int16x4_t b) { - return vqsub_s16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqsub_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> [[VQSUB_V_I]], <2 x i32> [[VQSUB_V1_I]]) -// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <2 x i32> [[VQSUB_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <2 x i32> -// CHECK-NEXT: ret <2 x i32> [[TMP2]] -// -int32x2_t test_vqsub_s32(int32x2_t a, int32x2_t b) { - return vqsub_s32(a, b); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vqsub_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqsub.v1i64(<1 x i64> [[VQSUB_V_I]], <1 x i64> [[VQSUB_V1_I]]) -// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <1 x i64> [[VQSUB_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to i64 -// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0 -// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] -// -int64x1_t test_vqsub_s64(int64x1_t a, int64x1_t b) { - return vqsub_s64(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vqsub_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSUB_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i8> [[VQSUB_V_I]] -// -uint8x8_t test_vqsub_u8(uint8x8_t a, uint8x8_t b) { - return vqsub_u8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqsub_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> [[VQSUB_V_I]], <4 x i16> [[VQSUB_V1_I]]) -// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <4 x i16> [[VQSUB_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <4 x i16> -// CHECK-NEXT: ret <4 x i16> [[TMP2]] -// -uint16x4_t test_vqsub_u16(uint16x4_t a, uint16x4_t b) { - return vqsub_u16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqsub_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> [[VQSUB_V_I]], <2 x i32> [[VQSUB_V1_I]]) -// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <2 x i32> [[VQSUB_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <2 x i32> -// CHECK-NEXT: ret <2 x i32> [[TMP2]] -// -uint32x2_t test_vqsub_u32(uint32x2_t a, uint32x2_t b) { - return vqsub_u32(a, b); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vqsub_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqsub.v1i64(<1 x i64> [[VQSUB_V_I]], <1 x i64> [[VQSUB_V1_I]]) -// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <1 x i64> [[VQSUB_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to i64 -// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0 -// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] -// -uint64x1_t test_vqsub_u64(uint64x1_t a, uint64x1_t b) { - return vqsub_u64(a, b); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqsubq_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) -// CHECK-NEXT: ret <16 x i8> [[VQSUBQ_V_I]] -// -int8x16_t test_vqsubq_s8(int8x16_t a, int8x16_t b) { - return vqsubq_s8(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqsubq_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> [[VQSUBQ_V_I]], <8 x i16> [[VQSUBQ_V1_I]]) -// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSUBQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[TMP2]] -// -int16x8_t test_vqsubq_s16(int16x8_t a, int16x8_t b) { - return vqsubq_s16(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqsubq_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQSUBQ_V_I]], <4 x i32> [[VQSUBQ_V1_I]]) -// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSUBQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[TMP2]] -// -int32x4_t test_vqsubq_s32(int32x4_t a, int32x4_t b) { - return vqsubq_s32(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqsubq_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQSUBQ_V_I]], <2 x i64> [[VQSUBQ_V1_I]]) -// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSUBQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <2 x i64> -// CHECK-NEXT: ret <2 x i64> [[TMP2]] -// -int64x2_t test_vqsubq_s64(int64x2_t a, int64x2_t b) { - return vqsubq_s64(a, b); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqsubq_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqsub.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) -// CHECK-NEXT: ret <16 x i8> [[VQSUBQ_V_I]] -// -uint8x16_t test_vqsubq_u8(uint8x16_t a, uint8x16_t b) { - return vqsubq_u8(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqsubq_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16> [[VQSUBQ_V_I]], <8 x i16> [[VQSUBQ_V1_I]]) -// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSUBQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[TMP2]] -// -uint16x8_t test_vqsubq_u16(uint16x8_t a, uint16x8_t b) { - return vqsubq_u16(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqsubq_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32> [[VQSUBQ_V_I]], <4 x i32> [[VQSUBQ_V1_I]]) -// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSUBQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[TMP2]] -// -uint32x4_t test_vqsubq_u32(uint32x4_t a, uint32x4_t b) { - return vqsubq_u32(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqsubq_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64> [[VQSUBQ_V_I]], <2 x i64> [[VQSUBQ_V1_I]]) -// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSUBQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <2 x i64> -// CHECK-NEXT: ret <2 x i64> [[TMP2]] -// -uint64x2_t test_vqsubq_u64(uint64x2_t a, uint64x2_t b) { - return vqsubq_u64(a, b); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vqshl_s8( // CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -5688,98 +5454,6 @@ uint64_t test_vqaddd_u64(uint64_t a, uint64_t b) { return vqaddd_u64(a, b); } -// CHECK-LABEL: define dso_local i8 @test_vqsubb_s8( -// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -// CHECK-NEXT: [[VQSUBB_S8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSUBB_S8_I]], i64 0 -// CHECK-NEXT: ret i8 [[TMP2]] -// -int8_t test_vqsubb_s8(int8_t a, int8_t b) { - return vqsubb_s8(a, b); -} - -// CHECK-LABEL: define dso_local i16 @test_vqsubh_s16( -// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 -// CHECK-NEXT: [[VQSUBH_S16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSUBH_S16_I]], i64 0 -// CHECK-NEXT: ret i16 [[TMP2]] -// -int16_t test_vqsubh_s16(int16_t a, int16_t b) { - return vqsubh_s16(a, b); -} - -// CHECK-LABEL: define dso_local i32 @test_vqsubs_s32( -// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSUBS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqsub.i32(i32 [[A]], i32 [[B]]) -// CHECK-NEXT: ret i32 [[VQSUBS_S32_I]] -// -int32_t test_vqsubs_s32(int32_t a, int32_t b) { - return vqsubs_s32(a, b); -} - -// CHECK-LABEL: define dso_local i64 @test_vqsubd_s64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSUBD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sqsub.i64(i64 [[A]], i64 [[B]]) -// CHECK-NEXT: ret i64 [[VQSUBD_S64_I]] -// -int64_t test_vqsubd_s64(int64_t a, int64_t b) { - return vqsubd_s64(a, b); -} - -// CHECK-LABEL: define dso_local i8 @test_vqsubb_u8( -// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -// CHECK-NEXT: [[VQSUBB_U8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSUBB_U8_I]], i64 0 -// CHECK-NEXT: ret i8 [[TMP2]] -// -uint8_t test_vqsubb_u8(uint8_t a, uint8_t b) { - return vqsubb_u8(a, b); -} - -// CHECK-LABEL: define dso_local i16 @test_vqsubh_u16( -// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 -// CHECK-NEXT: [[VQSUBH_U16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSUBH_U16_I]], i64 0 -// CHECK-NEXT: ret i16 [[TMP2]] -// -uint16_t test_vqsubh_u16(uint16_t a, uint16_t b) { - return vqsubh_u16(a, b); -} - -// CHECK-LABEL: define dso_local i32 @test_vqsubs_u32( -// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSUBS_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uqsub.i32(i32 [[A]], i32 [[B]]) -// CHECK-NEXT: ret i32 [[VQSUBS_U32_I]] -// -uint32_t test_vqsubs_u32(uint32_t a, uint32_t b) { - return vqsubs_u32(a, b); -} - -// CHECK-LABEL: define dso_local i64 @test_vqsubd_u64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSUBD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.uqsub.i64(i64 [[A]], i64 [[B]]) -// CHECK-NEXT: ret i64 [[VQSUBD_U64_I]] -// -uint64_t test_vqsubd_u64(uint64_t a, uint64_t b) { - return vqsubd_u64(a, b); -} - // CHECK-LABEL: define dso_local i8 @test_vqshlb_s8( // CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/subtraction.c b/clang/test/CodeGen/AArch64/neon/subtraction.c index 31f74267fd1b8..952d1f76b53d6 100644 --- a/clang/test/CodeGen/AArch64/neon/subtraction.c +++ b/clang/test/CodeGen/AArch64/neon/subtraction.c @@ -1084,3 +1084,370 @@ uint32x4_t test_vrsubhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b) { // LLVM: ret <4 x i32> [[RES]] return vrsubhn_high_u64(r, a, b); } + +//===------------------------------------------------------===// +// 2.1.1.5.4. Saturating subtract +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#saturating-subtract +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vqsub_s8( +// CIR-LABEL: @vqsub_s8( +int8x8_t test_vqsub_s8(int8x8_t a, int8x8_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> + +// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[VQSUB_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM: ret <8 x i8> [[VQSUB_V_I]] + return vqsub_s8(a, b); +} + +// LLVM-LABEL: @test_vqsub_s16( +// CIR-LABEL: @vqsub_s16( +int16x4_t test_vqsub_s16(int16x4_t a, int16x4_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> + +// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM: [[VQSUB_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> [[VQSUB_V_I]], <4 x i16> [[VQSUB_V1_I]]) +// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <4 x i16> [[VQSUB_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <4 x i16> +// LLVM: ret <4 x i16> [[TMP2]] + return vqsub_s16(a, b); +} + +// LLVM-LABEL: @test_vqsub_s32( +// CIR-LABEL: @vqsub_s32( +int32x2_t test_vqsub_s32(int32x2_t a, int32x2_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s32i> + +// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM: [[VQSUB_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> [[VQSUB_V_I]], <2 x i32> [[VQSUB_V1_I]]) +// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <2 x i32> [[VQSUB_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <2 x i32> +// LLVM: ret <2 x i32> [[TMP2]] + return vqsub_s32(a, b); +} + +// LLVM-LABEL: @test_vqsub_s64( +// CIR-LABEL: @vqsub_s64( +int64x1_t test_vqsub_s64(int64x1_t a, int64x1_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>) -> !cir.vector<1 x !s64i> + +// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> +// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> +// LLVM: [[VQSUB_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqsub.v1i64(<1 x i64> [[VQSUB_V_I]], <1 x i64> [[VQSUB_V1_I]]) +// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <1 x i64> [[VQSUB_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to i64 +// LLVM: [[INS:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 0 +// LLVM: ret <1 x i64> [[INS]] + return vqsub_s64(a, b); +} + +// LLVM-LABEL: @test_vqsub_u8( +// CIR-LABEL: @vqsub_u8( +uint8x8_t test_vqsub_u8(uint8x8_t a, uint8x8_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> + +// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[VQSUB_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM: ret <8 x i8> [[VQSUB_V_I]] + return vqsub_u8(a, b); +} + +// LLVM-LABEL: @test_vqsub_u16( +// CIR-LABEL: @vqsub_u16( +uint16x4_t test_vqsub_u16(uint16x4_t a, uint16x4_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> + +// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM: [[VQSUB_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> [[VQSUB_V_I]], <4 x i16> [[VQSUB_V1_I]]) +// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <4 x i16> [[VQSUB_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <4 x i16> +// LLVM: ret <4 x i16> [[TMP2]] + return vqsub_u16(a, b); +} + +// LLVM-LABEL: @test_vqsub_u32( +// CIR-LABEL: @vqsub_u32( +uint32x2_t test_vqsub_u32(uint32x2_t a, uint32x2_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u32i> + +// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM: [[VQSUB_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> [[VQSUB_V_I]], <2 x i32> [[VQSUB_V1_I]]) +// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <2 x i32> [[VQSUB_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <2 x i32> +// LLVM: ret <2 x i32> [[TMP2]] + return vqsub_u32(a, b); +} + +// LLVM-LABEL: @test_vqsub_u64( +// CIR-LABEL: @vqsub_u64( +uint64x1_t test_vqsub_u64(uint64x1_t a, uint64x1_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>) -> !cir.vector<1 x !u64i> + +// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> +// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> +// LLVM: [[VQSUB_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqsub.v1i64(<1 x i64> [[VQSUB_V_I]], <1 x i64> [[VQSUB_V1_I]]) +// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <1 x i64> [[VQSUB_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to i64 +// LLVM: [[INS:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 0 +// LLVM: ret <1 x i64> [[INS]] + return vqsub_u64(a, b); +} + +// LLVM-LABEL: @test_vqsubq_s8( +// CIR-LABEL: @vqsubq_s8( +int8x16_t test_vqsubq_s8(int8x16_t a, int8x16_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> + +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[VQSUBQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) +// LLVM: ret <16 x i8> [[VQSUBQ_V_I]] + return vqsubq_s8(a, b); +} + +// LLVM-LABEL: @test_vqsubq_s16( +// CIR-LABEL: @vqsubq_s16( +int16x8_t test_vqsubq_s16(int16x8_t a, int16x8_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>) -> !cir.vector<8 x !s16i> + +// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> +// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> +// LLVM: [[VQSUBQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> [[VQSUBQ_V_I]], <8 x i16> [[VQSUBQ_V1_I]]) +// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSUBQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <8 x i16> +// LLVM: ret <8 x i16> [[TMP2]] + return vqsubq_s16(a, b); +} + +// LLVM-LABEL: @test_vqsubq_s32( +// CIR-LABEL: @vqsubq_s32( +int32x4_t test_vqsubq_s32(int32x4_t a, int32x4_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> + +// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> +// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// LLVM: [[VQSUBQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQSUBQ_V_I]], <4 x i32> [[VQSUBQ_V1_I]]) +// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSUBQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <4 x i32> +// LLVM: ret <4 x i32> [[TMP2]] + return vqsubq_s32(a, b); +} + +// LLVM-LABEL: @test_vqsubq_s64( +// CIR-LABEL: @vqsubq_s64( +int64x2_t test_vqsubq_s64(int64x2_t a, int64x2_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>) -> !cir.vector<2 x !s64i> + +// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> +// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// LLVM: [[VQSUBQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQSUBQ_V_I]], <2 x i64> [[VQSUBQ_V1_I]]) +// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSUBQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <2 x i64> +// LLVM: ret <2 x i64> [[TMP2]] + return vqsubq_s64(a, b); +} + +// LLVM-LABEL: @test_vqsubq_u8( +// CIR-LABEL: @vqsubq_u8( +uint8x16_t test_vqsubq_u8(uint8x16_t a, uint8x16_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>) -> !cir.vector<16 x !u8i> + +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[VQSUBQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqsub.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) +// LLVM: ret <16 x i8> [[VQSUBQ_V_I]] + return vqsubq_u8(a, b); +} + +// LLVM-LABEL: @test_vqsubq_u16( +// CIR-LABEL: @vqsubq_u16( +uint16x8_t test_vqsubq_u16(uint16x8_t a, uint16x8_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>) -> !cir.vector<8 x !u16i> + +// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> +// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> +// LLVM: [[VQSUBQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16> [[VQSUBQ_V_I]], <8 x i16> [[VQSUBQ_V1_I]]) +// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSUBQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <8 x i16> +// LLVM: ret <8 x i16> [[TMP2]] + return vqsubq_u16(a, b); +} + +// LLVM-LABEL: @test_vqsubq_u32( +// CIR-LABEL: @vqsubq_u32( +uint32x4_t test_vqsubq_u32(uint32x4_t a, uint32x4_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>) -> !cir.vector<4 x !u32i> + +// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> +// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// LLVM: [[VQSUBQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32> [[VQSUBQ_V_I]], <4 x i32> [[VQSUBQ_V1_I]]) +// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSUBQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <4 x i32> +// LLVM: ret <4 x i32> [[TMP2]] + return vqsubq_u32(a, b); +} + +// LLVM-LABEL: @test_vqsubq_u64( +// CIR-LABEL: @vqsubq_u64( +uint64x2_t test_vqsubq_u64(uint64x2_t a, uint64x2_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !u64i> + +// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> +// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// LLVM: [[VQSUBQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64> [[VQSUBQ_V_I]], <2 x i64> [[VQSUBQ_V1_I]]) +// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSUBQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <2 x i64> +// LLVM: ret <2 x i64> [[TMP2]] + return vqsubq_u64(a, b); +} + +// LLVM-LABEL: @test_vqsubs_s32( +// CIR-LABEL: @vqsubs_s32( +int32_t test_vqsubs_s32(int32_t a, int32_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!s32i, !s32i) -> !s32i + +// LLVM-SAME: i32 {{.*}} [[A:%.*]], i32 {{.*}} [[B:%.*]]) +// LLVM: [[VQSUBS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqsub.i32(i32 [[A]], i32 [[B]]) +// LLVM: ret i32 [[VQSUBS_S32_I]] + return vqsubs_s32(a, b); +} + +// LLVM-LABEL: @test_vqsubs_u32( +// CIR-LABEL: @vqsubs_u32( +uint32_t test_vqsubs_u32(uint32_t a, uint32_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!u32i, !u32i) -> !u32i + +// LLVM-SAME: i32 {{.*}} [[A:%.*]], i32 {{.*}} [[B:%.*]]) +// LLVM: [[VQSUBS_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uqsub.i32(i32 [[A]], i32 [[B]]) +// LLVM: ret i32 [[VQSUBS_U32_I]] + return vqsubs_u32(a, b); +} + +// LLVM-LABEL: @test_vqsubh_s16( +// CIR-LABEL: @vqsubh_s16( +int16_t test_vqsubh_s16(int16_t a, int16_t b) { +// CIR: [[INS0:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<4 x !s16i> +// CIR: [[INS1:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<4 x !s16i> +// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sqsub" [[INS0]], [[INS1]] : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> +// CIR: {{%.*}} = cir.vec.extract [[RES]][{{%.*}} : !u64i] : !cir.vector<4 x !s16i> + +// LLVM-SAME: i16 {{.*}} [[A:%.*]], i16 {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 +// LLVM: [[VQSUBH_S16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// LLVM: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSUBH_S16_I]], i64 0 +// LLVM: ret i16 [[TMP2]] + return vqsubh_s16(a, b); +} + +// LLVM-LABEL: @test_vqsubh_u16( +// CIR-LABEL: @vqsubh_u16( +uint16_t test_vqsubh_u16(uint16_t a, uint16_t b) { +// CIR: [[INS0:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<4 x !u16i> +// CIR: [[INS1:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<4 x !u16i> +// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.uqsub" [[INS0]], [[INS1]] : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> +// CIR: {{%.*}} = cir.vec.extract [[RES]][{{%.*}} : !u64i] : !cir.vector<4 x !u16i> + +// LLVM-SAME: i16 {{.*}} [[A:%.*]], i16 {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 +// LLVM: [[VQSUBH_U16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// LLVM: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSUBH_U16_I]], i64 0 +// LLVM: ret i16 [[TMP2]] + return vqsubh_u16(a, b); +} + +// LLVM-LABEL: @test_vqsubb_s8( +// CIR-LABEL: @vqsubb_s8( +int8_t test_vqsubb_s8(int8_t a, int8_t b) { +// CIR: [[INS0:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<8 x !s8i> +// CIR: [[INS1:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<8 x !s8i> +// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sqsub" [[INS0]], [[INS1]] : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> +// CIR: {{%.*}} = cir.vec.extract [[RES]][{{%.*}} : !u64i] : !cir.vector<8 x !s8i> + +// LLVM-SAME: i8 {{.*}} [[A:%.*]], i8 {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 +// LLVM: [[VQSUBB_S8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) +// LLVM: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSUBB_S8_I]], i64 0 +// LLVM: ret i8 [[TMP2]] + return vqsubb_s8(a, b); +} + +// LLVM-LABEL: @test_vqsubb_u8( +// CIR-LABEL: @vqsubb_u8( +uint8_t test_vqsubb_u8(uint8_t a, uint8_t b) { +// CIR: [[INS0:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<8 x !u8i> +// CIR: [[INS1:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<8 x !u8i> +// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.uqsub" [[INS0]], [[INS1]] : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> +// CIR: {{%.*}} = cir.vec.extract [[RES]][{{%.*}} : !u64i] : !cir.vector<8 x !u8i> + +// LLVM-SAME: i8 {{.*}} [[A:%.*]], i8 {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 +// LLVM: [[VQSUBB_U8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) +// LLVM: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSUBB_U8_I]], i64 0 +// LLVM: ret i8 [[TMP2]] + return vqsubb_u8(a, b); +} + +// LLVM-LABEL: @test_vqsubd_s64( +// CIR-LABEL: @vqsubd_s64( +int64_t test_vqsubd_s64(int64_t a, int64_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!s64i, !s64i) -> !s64i + +// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) +// LLVM: [[VQSUBD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sqsub.i64(i64 [[A]], i64 [[B]]) +// LLVM: ret i64 [[VQSUBD_S64_I]] + return vqsubd_s64(a, b); +} + +// LLVM-LABEL: @test_vqsubd_u64( +// CIR-LABEL: @vqsubd_u64( +uint64_t test_vqsubd_u64(uint64_t a, uint64_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!u64i, !u64i) -> !u64i + +// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) +// LLVM: [[VQSUBD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.uqsub.i64(i64 [[A]], i64 [[B]]) +// LLVM: ret i64 [[VQSUBD_U64_I]] + return vqsubd_u64(a, b); +} >From 2207a39a34a099850e56b00111ae01610a227193 Mon Sep 17 00:00:00 2001 From: E00N777 <[email protected]> Date: Sun, 19 Jul 2026 14:56:22 +0800 Subject: [PATCH 2/2] Narrow this PR's scope by dropping the SISD intrinsics --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 32 +-- clang/test/CodeGen/AArch64/neon-intrinsics.c | 92 +++++++ clang/test/CodeGen/AArch64/neon/subtraction.c | 236 ++---------------- 3 files changed, 119 insertions(+), 241 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 1b2db4a35021e..92b8c61ac38ad 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -470,14 +470,6 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( case NEON::BI__builtin_neon_vpmaxnms_f32: case NEON::BI__builtin_neon_vpmaxnmqd_f64: case NEON::BI__builtin_neon_vmulxh_f16: - case NEON::BI__builtin_neon_vqsubs_s32: - case NEON::BI__builtin_neon_vqsubs_u32: - case NEON::BI__builtin_neon_vqsubd_s64: - case NEON::BI__builtin_neon_vqsubd_u64: - case NEON::BI__builtin_neon_vqsubb_s8: - case NEON::BI__builtin_neon_vqsubb_u8: - case NEON::BI__builtin_neon_vqsubh_s16: - case NEON::BI__builtin_neon_vqsubh_u16: break; } @@ -491,28 +483,8 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( auto [funcResTy, argTypes] = deriveNeonSISDIntrinsicOperandTypes( cgf, info.TypeModifier, arg0Ty, resultTy, ops); - // Scalar operands feeding a vector `argType` (e.g. vqsubb_s8, which has no - // scalar overload) are splatted into lane 0 of a poison vector. - for (unsigned i = 0, e = ops.size(); i != e; ++i) { - auto vecArgTy = mlir::dyn_cast<cir::VectorType>(argTypes[i]); - if (vecArgTy && !mlir::isa<cir::VectorType>(ops[i].getType()) && - cgf.cgm.getDataLayout().getTypeSizeInBits(ops[i].getType()) != - cgf.cgm.getDataLayout().getTypeSizeInBits(vecArgTy)) { - mlir::Value poison = - builder.getConstant(loc, cir::PoisonAttr::get(vecArgTy)); - ops[i] = builder.createInsertElement(loc, poison, ops[i], /*idx=*/0); - } - } - - mlir::Value result = emitNeonCall(cgf.cgm, builder, std::move(argTypes), ops, - llvmIntrName, funcResTy, loc); - - // Recover a scalar result from a wider vector intrinsic result via lane 0. - if (auto resVecTy = mlir::dyn_cast<cir::VectorType>(result.getType()); - resVecTy && cgf.cgm.getDataLayout().getTypeSizeInBits(resultTy) < - cgf.cgm.getDataLayout().getTypeSizeInBits(resVecTy)) - return builder.createExtractElement(loc, result, /*idx=*/0); - return result; + return emitNeonCall(cgf.cgm, builder, std::move(argTypes), ops, llvmIntrName, + funcResTy, loc); } //===----------------------------------------------------------------------===// diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 2afa1f6119ca1..e268d60f2be16 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -5454,6 +5454,98 @@ uint64_t test_vqaddd_u64(uint64_t a, uint64_t b) { return vqaddd_u64(a, b); } +// CHECK-LABEL: define dso_local i8 @test_vqsubb_s8( +// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 +// CHECK-NEXT: [[VQSUBB_S8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSUBB_S8_I]], i64 0 +// CHECK-NEXT: ret i8 [[TMP2]] +// +int8_t test_vqsubb_s8(int8_t a, int8_t b) { + return vqsubb_s8(a, b); +} + +// CHECK-LABEL: define dso_local i16 @test_vqsubh_s16( +// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 +// CHECK-NEXT: [[VQSUBH_S16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSUBH_S16_I]], i64 0 +// CHECK-NEXT: ret i16 [[TMP2]] +// +int16_t test_vqsubh_s16(int16_t a, int16_t b) { + return vqsubh_s16(a, b); +} + +// CHECK-LABEL: define dso_local i32 @test_vqsubs_s32( +// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[VQSUBS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqsub.i32(i32 [[A]], i32 [[B]]) +// CHECK-NEXT: ret i32 [[VQSUBS_S32_I]] +// +int32_t test_vqsubs_s32(int32_t a, int32_t b) { + return vqsubs_s32(a, b); +} + +// CHECK-LABEL: define dso_local i64 @test_vqsubd_s64( +// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[VQSUBD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sqsub.i64(i64 [[A]], i64 [[B]]) +// CHECK-NEXT: ret i64 [[VQSUBD_S64_I]] +// +int64_t test_vqsubd_s64(int64_t a, int64_t b) { + return vqsubd_s64(a, b); +} + +// CHECK-LABEL: define dso_local i8 @test_vqsubb_u8( +// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 +// CHECK-NEXT: [[VQSUBB_U8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSUBB_U8_I]], i64 0 +// CHECK-NEXT: ret i8 [[TMP2]] +// +uint8_t test_vqsubb_u8(uint8_t a, uint8_t b) { + return vqsubb_u8(a, b); +} + +// CHECK-LABEL: define dso_local i16 @test_vqsubh_u16( +// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 +// CHECK-NEXT: [[VQSUBH_U16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSUBH_U16_I]], i64 0 +// CHECK-NEXT: ret i16 [[TMP2]] +// +uint16_t test_vqsubh_u16(uint16_t a, uint16_t b) { + return vqsubh_u16(a, b); +} + +// CHECK-LABEL: define dso_local i32 @test_vqsubs_u32( +// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[VQSUBS_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uqsub.i32(i32 [[A]], i32 [[B]]) +// CHECK-NEXT: ret i32 [[VQSUBS_U32_I]] +// +uint32_t test_vqsubs_u32(uint32_t a, uint32_t b) { + return vqsubs_u32(a, b); +} + +// CHECK-LABEL: define dso_local i64 @test_vqsubd_u64( +// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[VQSUBD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.uqsub.i64(i64 [[A]], i64 [[B]]) +// CHECK-NEXT: ret i64 [[VQSUBD_U64_I]] +// +uint64_t test_vqsubd_u64(uint64_t a, uint64_t b) { + return vqsubd_u64(a, b); +} + // CHECK-LABEL: define dso_local i8 @test_vqshlb_s8( // CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/subtraction.c b/clang/test/CodeGen/AArch64/neon/subtraction.c index 952d1f76b53d6..6613e7dbe0031 100644 --- a/clang/test/CodeGen/AArch64/neon/subtraction.c +++ b/clang/test/CodeGen/AArch64/neon/subtraction.c @@ -12,7 +12,7 @@ // ACLE section headings based on v2025Q2 of the ACLE specification: // * https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#subtract // -// TODO: Migrate Saturating subtract test cases. +// TODO: Migrate scalar saturating subtract test cases. // //============================================================================= @@ -1107,14 +1107,8 @@ int16x4_t test_vqsub_s16(int16x4_t a, int16x4_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// LLVM: [[VQSUB_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> [[VQSUB_V_I]], <4 x i16> [[VQSUB_V1_I]]) -// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <4 x i16> [[VQSUB_V2_I]] to <8 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <4 x i16> -// LLVM: ret <4 x i16> [[TMP2]] +// LLVM: [[VQSUB_V_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> [[A]], <4 x i16> [[B]]) +// LLVM: ret <4 x i16> [[VQSUB_V_I]] return vqsub_s16(a, b); } @@ -1124,14 +1118,8 @@ int32x2_t test_vqsub_s32(int32x2_t a, int32x2_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s32i> // LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// LLVM: [[VQSUB_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> [[VQSUB_V_I]], <2 x i32> [[VQSUB_V1_I]]) -// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <2 x i32> [[VQSUB_V2_I]] to <8 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <2 x i32> -// LLVM: ret <2 x i32> [[TMP2]] +// LLVM: [[VQSUB_V_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> [[A]], <2 x i32> [[B]]) +// LLVM: ret <2 x i32> [[VQSUB_V_I]] return vqsub_s32(a, b); } @@ -1141,15 +1129,8 @@ int64x1_t test_vqsub_s64(int64x1_t a, int64x1_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>) -> !cir.vector<1 x !s64i> // LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// LLVM: [[VQSUB_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqsub.v1i64(<1 x i64> [[VQSUB_V_I]], <1 x i64> [[VQSUB_V1_I]]) -// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <1 x i64> [[VQSUB_V2_I]] to <8 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to i64 -// LLVM: [[INS:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 0 -// LLVM: ret <1 x i64> [[INS]] +// LLVM: [[VQSUB_V_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqsub.v1i64(<1 x i64> [[A]], <1 x i64> [[B]]) +// LLVM: ret <1 x i64> [[VQSUB_V_I]] return vqsub_s64(a, b); } @@ -1170,14 +1151,8 @@ uint16x4_t test_vqsub_u16(uint16x4_t a, uint16x4_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// LLVM: [[VQSUB_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> [[VQSUB_V_I]], <4 x i16> [[VQSUB_V1_I]]) -// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <4 x i16> [[VQSUB_V2_I]] to <8 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <4 x i16> -// LLVM: ret <4 x i16> [[TMP2]] +// LLVM: [[VQSUB_V_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> [[A]], <4 x i16> [[B]]) +// LLVM: ret <4 x i16> [[VQSUB_V_I]] return vqsub_u16(a, b); } @@ -1187,14 +1162,8 @@ uint32x2_t test_vqsub_u32(uint32x2_t a, uint32x2_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u32i> // LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// LLVM: [[VQSUB_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> [[VQSUB_V_I]], <2 x i32> [[VQSUB_V1_I]]) -// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <2 x i32> [[VQSUB_V2_I]] to <8 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <2 x i32> -// LLVM: ret <2 x i32> [[TMP2]] +// LLVM: [[VQSUB_V_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> [[A]], <2 x i32> [[B]]) +// LLVM: ret <2 x i32> [[VQSUB_V_I]] return vqsub_u32(a, b); } @@ -1204,15 +1173,8 @@ uint64x1_t test_vqsub_u64(uint64x1_t a, uint64x1_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>) -> !cir.vector<1 x !u64i> // LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// LLVM: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// LLVM: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// LLVM: [[VQSUB_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqsub.v1i64(<1 x i64> [[VQSUB_V_I]], <1 x i64> [[VQSUB_V1_I]]) -// LLVM: [[VQSUB_V3_I:%.*]] = bitcast <1 x i64> [[VQSUB_V2_I]] to <8 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to i64 -// LLVM: [[INS:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 0 -// LLVM: ret <1 x i64> [[INS]] +// LLVM: [[VQSUB_V_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqsub.v1i64(<1 x i64> [[A]], <1 x i64> [[B]]) +// LLVM: ret <1 x i64> [[VQSUB_V_I]] return vqsub_u64(a, b); } @@ -1233,14 +1195,8 @@ int16x8_t test_vqsubq_s16(int16x8_t a, int16x8_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>) -> !cir.vector<8 x !s16i> // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// LLVM: [[VQSUBQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> [[VQSUBQ_V_I]], <8 x i16> [[VQSUBQ_V1_I]]) -// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSUBQ_V2_I]] to <16 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <8 x i16> -// LLVM: ret <8 x i16> [[TMP2]] +// LLVM: [[VQSUBQ_V_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> [[A]], <8 x i16> [[B]]) +// LLVM: ret <8 x i16> [[VQSUBQ_V_I]] return vqsubq_s16(a, b); } @@ -1250,14 +1206,8 @@ int32x4_t test_vqsubq_s32(int32x4_t a, int32x4_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> // LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// LLVM: [[VQSUBQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQSUBQ_V_I]], <4 x i32> [[VQSUBQ_V1_I]]) -// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSUBQ_V2_I]] to <16 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <4 x i32> -// LLVM: ret <4 x i32> [[TMP2]] +// LLVM: [[VQSUBQ_V_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) +// LLVM: ret <4 x i32> [[VQSUBQ_V_I]] return vqsubq_s32(a, b); } @@ -1267,14 +1217,8 @@ int64x2_t test_vqsubq_s64(int64x2_t a, int64x2_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>) -> !cir.vector<2 x !s64i> // LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// LLVM: [[VQSUBQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQSUBQ_V_I]], <2 x i64> [[VQSUBQ_V1_I]]) -// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSUBQ_V2_I]] to <16 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <2 x i64> -// LLVM: ret <2 x i64> [[TMP2]] +// LLVM: [[VQSUBQ_V_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[A]], <2 x i64> [[B]]) +// LLVM: ret <2 x i64> [[VQSUBQ_V_I]] return vqsubq_s64(a, b); } @@ -1295,14 +1239,8 @@ uint16x8_t test_vqsubq_u16(uint16x8_t a, uint16x8_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>) -> !cir.vector<8 x !u16i> // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// LLVM: [[VQSUBQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16> [[VQSUBQ_V_I]], <8 x i16> [[VQSUBQ_V1_I]]) -// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSUBQ_V2_I]] to <16 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <8 x i16> -// LLVM: ret <8 x i16> [[TMP2]] +// LLVM: [[VQSUBQ_V_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16> [[A]], <8 x i16> [[B]]) +// LLVM: ret <8 x i16> [[VQSUBQ_V_I]] return vqsubq_u16(a, b); } @@ -1312,14 +1250,8 @@ uint32x4_t test_vqsubq_u32(uint32x4_t a, uint32x4_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>) -> !cir.vector<4 x !u32i> // LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// LLVM: [[VQSUBQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32> [[VQSUBQ_V_I]], <4 x i32> [[VQSUBQ_V1_I]]) -// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSUBQ_V2_I]] to <16 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <4 x i32> -// LLVM: ret <4 x i32> [[TMP2]] +// LLVM: [[VQSUBQ_V_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) +// LLVM: ret <4 x i32> [[VQSUBQ_V_I]] return vqsubq_u32(a, b); } @@ -1329,125 +1261,7 @@ uint64x2_t test_vqsubq_u64(uint64x2_t a, uint64x2_t b) { // CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !u64i> // LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// LLVM: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// LLVM: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// LLVM: [[VQSUBQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64> [[VQSUBQ_V_I]], <2 x i64> [[VQSUBQ_V1_I]]) -// LLVM: [[VQSUBQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSUBQ_V2_I]] to <16 x i8> -// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <2 x i64> -// LLVM: ret <2 x i64> [[TMP2]] +// LLVM: [[VQSUBQ_V_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64> [[A]], <2 x i64> [[B]]) +// LLVM: ret <2 x i64> [[VQSUBQ_V_I]] return vqsubq_u64(a, b); } - -// LLVM-LABEL: @test_vqsubs_s32( -// CIR-LABEL: @vqsubs_s32( -int32_t test_vqsubs_s32(int32_t a, int32_t b) { -// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!s32i, !s32i) -> !s32i - -// LLVM-SAME: i32 {{.*}} [[A:%.*]], i32 {{.*}} [[B:%.*]]) -// LLVM: [[VQSUBS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqsub.i32(i32 [[A]], i32 [[B]]) -// LLVM: ret i32 [[VQSUBS_S32_I]] - return vqsubs_s32(a, b); -} - -// LLVM-LABEL: @test_vqsubs_u32( -// CIR-LABEL: @vqsubs_u32( -uint32_t test_vqsubs_u32(uint32_t a, uint32_t b) { -// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!u32i, !u32i) -> !u32i - -// LLVM-SAME: i32 {{.*}} [[A:%.*]], i32 {{.*}} [[B:%.*]]) -// LLVM: [[VQSUBS_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uqsub.i32(i32 [[A]], i32 [[B]]) -// LLVM: ret i32 [[VQSUBS_U32_I]] - return vqsubs_u32(a, b); -} - -// LLVM-LABEL: @test_vqsubh_s16( -// CIR-LABEL: @vqsubh_s16( -int16_t test_vqsubh_s16(int16_t a, int16_t b) { -// CIR: [[INS0:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<4 x !s16i> -// CIR: [[INS1:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<4 x !s16i> -// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sqsub" [[INS0]], [[INS1]] : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> -// CIR: {{%.*}} = cir.vec.extract [[RES]][{{%.*}} : !u64i] : !cir.vector<4 x !s16i> - -// LLVM-SAME: i16 {{.*}} [[A:%.*]], i16 {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 -// LLVM: [[VQSUBH_S16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) -// LLVM: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSUBH_S16_I]], i64 0 -// LLVM: ret i16 [[TMP2]] - return vqsubh_s16(a, b); -} - -// LLVM-LABEL: @test_vqsubh_u16( -// CIR-LABEL: @vqsubh_u16( -uint16_t test_vqsubh_u16(uint16_t a, uint16_t b) { -// CIR: [[INS0:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<4 x !u16i> -// CIR: [[INS1:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<4 x !u16i> -// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.uqsub" [[INS0]], [[INS1]] : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> -// CIR: {{%.*}} = cir.vec.extract [[RES]][{{%.*}} : !u64i] : !cir.vector<4 x !u16i> - -// LLVM-SAME: i16 {{.*}} [[A:%.*]], i16 {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 -// LLVM: [[VQSUBH_U16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) -// LLVM: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSUBH_U16_I]], i64 0 -// LLVM: ret i16 [[TMP2]] - return vqsubh_u16(a, b); -} - -// LLVM-LABEL: @test_vqsubb_s8( -// CIR-LABEL: @vqsubb_s8( -int8_t test_vqsubb_s8(int8_t a, int8_t b) { -// CIR: [[INS0:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<8 x !s8i> -// CIR: [[INS1:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<8 x !s8i> -// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sqsub" [[INS0]], [[INS1]] : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> -// CIR: {{%.*}} = cir.vec.extract [[RES]][{{%.*}} : !u64i] : !cir.vector<8 x !s8i> - -// LLVM-SAME: i8 {{.*}} [[A:%.*]], i8 {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// LLVM: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -// LLVM: [[VQSUBB_S8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) -// LLVM: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSUBB_S8_I]], i64 0 -// LLVM: ret i8 [[TMP2]] - return vqsubb_s8(a, b); -} - -// LLVM-LABEL: @test_vqsubb_u8( -// CIR-LABEL: @vqsubb_u8( -uint8_t test_vqsubb_u8(uint8_t a, uint8_t b) { -// CIR: [[INS0:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<8 x !u8i> -// CIR: [[INS1:%.*]] = cir.vec.insert {{%.*}}, {{%.*}}[{{%.*}} : !u64i] : !cir.vector<8 x !u8i> -// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.uqsub" [[INS0]], [[INS1]] : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> -// CIR: {{%.*}} = cir.vec.extract [[RES]][{{%.*}} : !u64i] : !cir.vector<8 x !u8i> - -// LLVM-SAME: i8 {{.*}} [[A:%.*]], i8 {{.*}} [[B:%.*]]) -// LLVM: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// LLVM: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -// LLVM: [[VQSUBB_U8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) -// LLVM: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSUBB_U8_I]], i64 0 -// LLVM: ret i8 [[TMP2]] - return vqsubb_u8(a, b); -} - -// LLVM-LABEL: @test_vqsubd_s64( -// CIR-LABEL: @vqsubd_s64( -int64_t test_vqsubd_s64(int64_t a, int64_t b) { -// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqsub" {{%.*}}, {{%.*}} : (!s64i, !s64i) -> !s64i - -// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) -// LLVM: [[VQSUBD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sqsub.i64(i64 [[A]], i64 [[B]]) -// LLVM: ret i64 [[VQSUBD_S64_I]] - return vqsubd_s64(a, b); -} - -// LLVM-LABEL: @test_vqsubd_u64( -// CIR-LABEL: @vqsubd_u64( -uint64_t test_vqsubd_u64(uint64_t a, uint64_t b) { -// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqsub" {{%.*}}, {{%.*}} : (!u64i, !u64i) -> !u64i - -// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) -// LLVM: [[VQSUBD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.uqsub.i64(i64 [[A]], i64 [[B]]) -// LLVM: ret i64 [[VQSUBD_U64_I]] - return vqsubd_u64(a, b); -} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
