================
@@ -2026,6 +2104,15 @@ def : ProcModel<"znver5", Znver4Model,
ProcessorFeatures.ZN5Features,
def : ProcModel<"znver6", Znver4Model, ProcessorFeatures.ZN6Features,
ProcessorFeatures.ZN6Tuning>;
+// Hygon CPUs.
+
+def : Proc<"c86-4g-m4", ProcessorFeatures.C864GM4Features,
+ ProcessorFeatures.C864GM4Tuning>;
+def : Proc<"c86-4g-m6", ProcessorFeatures.C864GM6Features,
+ ProcessorFeatures.C864GM6Tuning>;
+def : Proc<"c86-4g-m7", ProcessorFeatures.C864GM7Features,
----------------
RKSimon wrote:
Any thoughts to using an existing scheduler model? AFAICT M4/6 are pretty close
to Znver2 and M7 is close to Znver4
https://github.com/llvm/llvm-project/pull/187622
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