https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/184717
>From cf7017ea60dee055bf2211f92f273dab774c1aca Mon Sep 17 00:00:00 2001 From: Lei Huang <[email protected]> Date: Wed, 4 Mar 2026 20:08:17 -0500 Subject: [PATCH 1/5] [PowerPC] Add builtins for Post Quantum Cryptography Acceleration This patch implements Post Quantum Cryptography (PQC) Acceleration builtins for PowerPC's future ISA by ensuring that vector operations (vec_add, vec_sub, vec_mul, vec_mulh) correctly map to VSX instructions (xvadduwm, xvadduhm, xvsubuwm, xvsubuhm, xvmuluwm, xvmuluhm, xvmulhsw, xvmulhsh, xvmulhuw, xvmulhuh) when targeting mcpu=future. Also adds missing vec_mulh builtins: * vector short vec_mulh(vector signed short, vector signed short) * vector unsigned short vec_mulh(vector unsigned short, vector unsigned short) Assisted by AI. --- clang/include/clang/Basic/BuiltinsPPC.def | 2 + clang/lib/Basic/Targets/PPC.cpp | 4 + clang/lib/Basic/Targets/PPC.h | 1 + clang/lib/Headers/altivec.h | 12 ++ clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c | 98 ++++++++++++ llvm/include/llvm/IR/IntrinsicsPowerPC.td | 2 + llvm/lib/Target/PowerPC/PPC.td | 6 + llvm/lib/Target/PowerPC/PPCInstrFuture.td | 29 ++++ llvm/test/CodeGen/PowerPC/pqc-acceleration.ll | 151 ++++++++++++++++++ 9 files changed, 305 insertions(+) create mode 100644 clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c create mode 100644 llvm/test/CodeGen/PowerPC/pqc-acceleration.ll diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index 75d7d92c4f9d4..263f478a8b3c0 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -654,6 +654,8 @@ TARGET_BUILTIN(__builtin_altivec_vmulhsd, "V2LLiV2LLiV2LLi", "", "power10-vector") TARGET_BUILTIN(__builtin_altivec_vmulhud, "V2ULLiV2ULLiV2ULLi", "", "power10-vector") +TARGET_BUILTIN(__builtin_altivec_vmulhsh, "V8SsV8SsV8Ss", "", "isa-future-instructions") +TARGET_BUILTIN(__builtin_altivec_vmulhuh, "V8UsV8UsV8Us", "", "isa-future-instructions") // P10 Vector Expand with Mask built-ins. TARGET_BUILTIN(__builtin_altivec_vexpandbm, "V16UcV16Uc", "", "power10-vector") diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index a37a68ad91724..ccb6c7ba60b37 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -59,6 +59,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasP9Vector = true; } else if (Feature == "+power10-vector") { HasP10Vector = true; + } else if (Feature == "+isa-future-instructions") { + HasFutureVector = true; } else if (Feature == "+pcrelative-memops") { HasPCRelativeMemops = true; } else if (Feature == "+spe" || Feature == "+efpu2") { @@ -434,6 +436,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__POWER10_VECTOR__"); if (HasPCRelativeMemops) Builder.defineMacro("__PCREL__"); + if (HasFutureVector) + Builder.defineMacro("__FUTURE_VECTOR__"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h index 664c9e15d8d18..0c71b8c3adfb0 100644 --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -69,6 +69,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool HasFrsqrte = false; bool HasFrsqrtes = false; bool HasP10Vector = false; + bool HasFutureVector = false; bool HasPCRelativeMemops = false; bool HasQuadwordAtomics = false; bool UseLongCalls = false; diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h index 71d8d3c0c0771..15c5c2d1962b6 100644 --- a/clang/lib/Headers/altivec.h +++ b/clang/lib/Headers/altivec.h @@ -6404,6 +6404,18 @@ vec_mulh(vector unsigned long long __a, vector unsigned long long __b) { } #endif +#ifdef __FUTURE_VECTOR__ +static __inline__ vector signed short __ATTRS_o_ai +vec_mulh(vector signed short __a, vector signed short __b) { + return __builtin_altivec_vmulhsh(__a, __b); +} + +static __inline__ vector unsigned short __ATTRS_o_ai +vec_mulh(vector unsigned short __a, vector unsigned short __b) { + return __builtin_altivec_vmulhuh(__a, __b); +} +#endif + /* vec_mulo */ static __inline__ vector short __ATTRS_o_ai vec_mulo(vector signed char __a, diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c b/clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c new file mode 100644 index 0000000000000..edd14530f39ef --- /dev/null +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c @@ -0,0 +1,98 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx \ +// RUN: -target-feature +isa-future-instructions -target-cpu future \ +// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s \ +// RUN: -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx \ +// RUN: -target-feature +isa-future-instructions -target-cpu future \ +// RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s \ +// RUN: -o - | FileCheck %s + +#include <altivec.h> + +vector unsigned int vuia, vuib; +vector unsigned short vusa, vusb; +vector signed int vsia, vsib; +vector signed short vssa, vssb; + +// Test vec_add for unsigned int +vector unsigned int test_vec_add_ui(void) { + // CHECK-LABEL: @test_vec_add_ui + // CHECK: add <4 x i32> + // CHECK-NEXT: ret <4 x i32> + return vec_add(vuia, vuib); +} + +// Test vec_add for unsigned short +vector unsigned short test_vec_add_uh(void) { + // CHECK-LABEL: @test_vec_add_uh + // CHECK: add <8 x i16> + // CHECK-NEXT: ret <8 x i16> + return vec_add(vusa, vusb); +} + +// Test vec_sub for unsigned int +vector unsigned int test_vec_sub_ui(void) { + // CHECK-LABEL: @test_vec_sub_ui + // CHECK: sub <4 x i32> + // CHECK-NEXT: ret <4 x i32> + return vec_sub(vuia, vuib); +} + +// Test vec_sub for unsigned short +vector unsigned short test_vec_sub_uh(void) { + // CHECK-LABEL: @test_vec_sub_uh + // CHECK: sub <8 x i16> + // CHECK-NEXT: ret <8 x i16> + return vec_sub(vusa, vusb); +} + +// Test vec_mul for unsigned int +vector unsigned int test_vec_mul_ui(void) { + // CHECK-LABEL: @test_vec_mul_ui + // CHECK: mul <4 x i32> + // CHECK-NEXT: ret <4 x i32> + return vec_mul(vuia, vuib); +} + +// Test vec_mul for unsigned short +vector unsigned short test_vec_mul_uh(void) { + // CHECK-LABEL: @test_vec_mul_uh + // CHECK: mul <8 x i16> + // CHECK-NEXT: ret <8 x i16> + return vec_mul(vusa, vusb); +} + +// Test vec_mulh for signed int +vector signed int test_vec_mulh_si(void) { + // CHECK-LABEL: @test_vec_mulh_si + // CHECK: call <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}) + // CHECK-NEXT: ret <4 x i32> + return vec_mulh(vsia, vsib); +} + +// Test vec_mulh for unsigned int +vector unsigned int test_vec_mulh_ui(void) { + // CHECK-LABEL: @test_vec_mulh_ui + // CHECK: call <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}) + // CHECK-NEXT: ret <4 x i32> + return vec_mulh(vuia, vuib); +} + +// Test vec_mulh for signed short +vector signed short test_vec_mulh_ss(void) { + // CHECK-LABEL: @test_vec_mulh_ss + // CHECK: call <8 x i16> @llvm.ppc.altivec.vmulhsh(<8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}) + // CHECK-NEXT: ret <8 x i16> + return vec_mulh(vssa, vssb); +} + +// Test vec_mulh for unsigned short +vector unsigned short test_vec_mulh_uh(void) { + // CHECK-LABEL: @test_vec_mulh_uh + // CHECK: call <8 x i16> @llvm.ppc.altivec.vmulhuh(<8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}) + // CHECK-NEXT: ret <8 x i16> + return vec_mulh(vusa, vusb); +} + +// Made with Bob diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index ec33af88c72d9..afa7de3966f8c 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -1362,6 +1362,8 @@ def int_ppc_altivec_vmulhsw : PowerPC_Vec_WWW_Intrinsic<"vmulhsw">; def int_ppc_altivec_vmulhuw : PowerPC_Vec_WWW_Intrinsic<"vmulhuw">; def int_ppc_altivec_vmulhsd : PowerPC_Vec_DDD_Intrinsic<"vmulhsd">; def int_ppc_altivec_vmulhud : PowerPC_Vec_DDD_Intrinsic<"vmulhud">; +def int_ppc_altivec_vmulhsh : PowerPC_Vec_HHH_Intrinsic<"vmulhsh">; +def int_ppc_altivec_vmulhuh : PowerPC_Vec_HHH_Intrinsic<"vmulhuh">; //===----------------------------------------------------------------------===// // PowerPC VSX Intrinsic Definitions. diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index c0abbf6f50804..b4f1c422a7f27 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -292,6 +292,10 @@ def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", "true", "Enable POWER10 vector instructions", [FeatureISA3_1, FeatureP9Vector]>; +def FeatureFutureVector : SubtargetFeature<"future-vector", "HasFutureVector", + "true", + "Enable Future vector instructions", + [FeatureISAFuture, FeatureP10Vector]>; // A separate feature for this even though it is equivalent to P9Vector // because this is a feature of the implementation rather than the architecture // and may go away with future CPU's. @@ -400,6 +404,7 @@ def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">; def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">; def NoP10Vector : Predicate<"!Subtarget->hasP10Vector()">; def HasP10Vector : Predicate<"Subtarget->hasP10Vector()">; +def HasFutureVector : Predicate<"Subtarget->hasFutureVector()">; // Predicates used to differenciate between different ISAs. def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; @@ -554,6 +559,7 @@ def ProcessorFeatures { // For future CPU we assume that all of the existing features from Power11 // still exist with the exception of those we know are Power11 specific. list<SubtargetFeature> FutureAdditionalFeatures = [DirectivePwrFuture, + FeatureFutureVector, FeatureISAFuture]; list<SubtargetFeature> FutureSpecificFeatures = []; list<SubtargetFeature> FutureInheritableFeatures = diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index 717454f78e2a4..18b5b523d2919 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -599,6 +599,35 @@ def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp, let Predicates = [HasVSX, IsISAFuture] in { def : Pat<(v4i32 (rotl v4i32:$vA, v4i32:$vB)), (v4i32 (XVRLW v4i32:$vA, v4i32:$vB))>; + + // Post Quantum Cryptography Acceleration patterns + // Use AddedComplexity to prefer these patterns over AltiVec patterns + let AddedComplexity = 400 in { + // Vector add + def : Pat<(v4i32 (add v4i32:$XA, v4i32:$XB)), (v4i32 (XVADDUWM $XA, $XB))>; + def : Pat<(v8i16 (add v8i16:$XA, v8i16:$XB)), + (COPY_TO_REGCLASS (XVADDUHM RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; + + // Vector subtract + def : Pat<(v4i32 (sub v4i32:$XA, v4i32:$XB)), (v4i32 (XVSUBUWM $XA, $XB))>; + def : Pat<(v8i16 (sub v8i16:$XA, v8i16:$XB)), + (COPY_TO_REGCLASS (XVSUBUHM RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; + + // Vector multiply + def : Pat<(v4i32 (mul v4i32:$XA, v4i32:$XB)), (v4i32 (XVMULUWM $XA, $XB))>; + def : Pat<(v8i16 (mul v8i16:$XA, v8i16:$XB)), + (COPY_TO_REGCLASS (XVMULUHM RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; + + // Vector multiply high intrinsics + def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$XA, v4i32:$XB)), + (v4i32 (XVMULHSW $XA, $XB))>; + def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$XA, v4i32:$XB)), + (v4i32 (XVMULHUW $XA, $XB))>; + def : Pat<(v8i16 (int_ppc_altivec_vmulhsh v8i16:$XA, v8i16:$XB)), + (COPY_TO_REGCLASS (XVMULHSH RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; + def : Pat<(v8i16 (int_ppc_altivec_vmulhuh v8i16:$XA, v8i16:$XB)), + (COPY_TO_REGCLASS (XVMULHUH RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; + } } //---------------------------- Instruction aliases ---------------------------// diff --git a/llvm/test/CodeGen/PowerPC/pqc-acceleration.ll b/llvm/test/CodeGen/PowerPC/pqc-acceleration.ll new file mode 100644 index 0000000000000..176e9785c1cad --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pqc-acceleration.ll @@ -0,0 +1,151 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=future < %s | FileCheck %s --check-prefix=CHECK-LE +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -mcpu=future < %s | FileCheck %s --check-prefix=CHECK-BE + +; Test Post Quantum Cryptography Acceleration instructions + +define <4 x i32> @test_xvadduwm(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LE-LABEL: test_xvadduwm: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: xvadduwm 34, 34, 35 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test_xvadduwm: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: xvadduwm 34, 34, 35 +; CHECK-BE-NEXT: blr + %res = add <4 x i32> %a, %b + ret <4 x i32> %res +} + +define <8 x i16> @test_xvadduhm(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LE-LABEL: test_xvadduhm: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: xvadduhm 34, 34, 35 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test_xvadduhm: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: xvadduhm 34, 34, 35 +; CHECK-BE-NEXT: blr + %res = add <8 x i16> %a, %b + ret <8 x i16> %res +} + +define <4 x i32> @test_xvsubuwm(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LE-LABEL: test_xvsubuwm: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: xvsubuwm 34, 34, 35 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test_xvsubuwm: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: xvsubuwm 34, 34, 35 +; CHECK-BE-NEXT: blr + %res = sub <4 x i32> %a, %b + ret <4 x i32> %res +} + +define <8 x i16> @test_xvsubuhm(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LE-LABEL: test_xvsubuhm: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: xvsubuhm 34, 34, 35 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test_xvsubuhm: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: xvsubuhm 34, 34, 35 +; CHECK-BE-NEXT: blr + %res = sub <8 x i16> %a, %b + ret <8 x i16> %res +} + +define <4 x i32> @test_xvmuluwm(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LE-LABEL: test_xvmuluwm: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: xvmuluwm 34, 34, 35 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test_xvmuluwm: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: xvmuluwm 34, 34, 35 +; CHECK-BE-NEXT: blr + %res = mul <4 x i32> %a, %b + ret <4 x i32> %res +} + +define <8 x i16> @test_xvmuluhm(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LE-LABEL: test_xvmuluhm: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: xvmuluhm 34, 34, 35 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test_xvmuluhm: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: xvmuluhm 34, 34, 35 +; CHECK-BE-NEXT: blr + %res = mul <8 x i16> %a, %b + ret <8 x i16> %res +} + +declare <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32>, <4 x i32>) +define <4 x i32> @test_xvmulhsw(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LE-LABEL: test_xvmulhsw: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: xvmulhsw 34, 34, 35 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test_xvmulhsw: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: xvmulhsw 34, 34, 35 +; CHECK-BE-NEXT: blr + %res = call <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +declare <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32>, <4 x i32>) +define <4 x i32> @test_xvmulhuw(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LE-LABEL: test_xvmulhuw: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: xvmulhuw 34, 34, 35 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test_xvmulhuw: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: xvmulhuw 34, 34, 35 +; CHECK-BE-NEXT: blr + %res = call <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +declare <8 x i16> @llvm.ppc.altivec.vmulhsh(<8 x i16>, <8 x i16>) +define <8 x i16> @test_xvmulhsh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LE-LABEL: test_xvmulhsh: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: xvmulhsh 34, 34, 35 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test_xvmulhsh: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: xvmulhsh 34, 34, 35 +; CHECK-BE-NEXT: blr + %res = call <8 x i16> @llvm.ppc.altivec.vmulhsh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +declare <8 x i16> @llvm.ppc.altivec.vmulhuh(<8 x i16>, <8 x i16>) +define <8 x i16> @test_xvmulhuh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LE-LABEL: test_xvmulhuh: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: xvmulhuh 34, 34, 35 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test_xvmulhuh: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: xvmulhuh 34, 34, 35 +; CHECK-BE-NEXT: blr + %res = call <8 x i16> @llvm.ppc.altivec.vmulhuh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} >From b6b085d655627e79c800658d1b71cc7c5796738f Mon Sep 17 00:00:00 2001 From: Lei Huang <[email protected]> Date: Wed, 4 Mar 2026 20:16:06 -0500 Subject: [PATCH 2/5] fix doc --- clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c b/clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c index edd14530f39ef..59ee466259c0e 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c @@ -8,6 +8,8 @@ // RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s \ // RUN: -o - | FileCheck %s +// AI Generated. + #include <altivec.h> vector unsigned int vuia, vuib; @@ -94,5 +96,3 @@ vector unsigned short test_vec_mulh_uh(void) { // CHECK-NEXT: ret <8 x i16> return vec_mulh(vusa, vusb); } - -// Made with Bob >From d6c0b5bd5cc229a4ef0b30a9c835f380f5056d56 Mon Sep 17 00:00:00 2001 From: Lei Huang <[email protected]> Date: Wed, 4 Mar 2026 20:20:11 -0500 Subject: [PATCH 3/5] rename test files --- ...c.c => builtins-ppc-post-quantum-crypto.c} | 0 .../CodeGen/PowerPC/post-quantum-crypto.ll | 101 ++++++++++++ llvm/test/CodeGen/PowerPC/pqc-acceleration.ll | 151 ------------------ 3 files changed, 101 insertions(+), 151 deletions(-) rename clang/test/CodeGen/PowerPC/{builtins-ppc-pqc.c => builtins-ppc-post-quantum-crypto.c} (100%) create mode 100644 llvm/test/CodeGen/PowerPC/post-quantum-crypto.ll delete mode 100644 llvm/test/CodeGen/PowerPC/pqc-acceleration.ll diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c b/clang/test/CodeGen/PowerPC/builtins-ppc-post-quantum-crypto.c similarity index 100% rename from clang/test/CodeGen/PowerPC/builtins-ppc-pqc.c rename to clang/test/CodeGen/PowerPC/builtins-ppc-post-quantum-crypto.c diff --git a/llvm/test/CodeGen/PowerPC/post-quantum-crypto.ll b/llvm/test/CodeGen/PowerPC/post-quantum-crypto.ll new file mode 100644 index 0000000000000..92ad707c40879 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/post-quantum-crypto.ll @@ -0,0 +1,101 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=future < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -mcpu=future < %s | FileCheck %s + +; Test Post Quantum Cryptography Acceleration instructions + +define <4 x i32> @test_xvadduwm(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_xvadduwm: +; CHECK: # %bb.0: +; CHECK-NEXT: xvadduwm 34, 34, 35 +; CHECK-NEXT: blr + %res = add <4 x i32> %a, %b + ret <4 x i32> %res +} + +define <8 x i16> @test_xvadduhm(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_xvadduhm: +; CHECK: # %bb.0: +; CHECK-NEXT: xvadduhm 34, 34, 35 +; CHECK-NEXT: blr + %res = add <8 x i16> %a, %b + ret <8 x i16> %res +} + +define <4 x i32> @test_xvsubuwm(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_xvsubuwm: +; CHECK: # %bb.0: +; CHECK-NEXT: xvsubuwm 34, 34, 35 +; CHECK-NEXT: blr + %res = sub <4 x i32> %a, %b + ret <4 x i32> %res +} + +define <8 x i16> @test_xvsubuhm(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_xvsubuhm: +; CHECK: # %bb.0: +; CHECK-NEXT: xvsubuhm 34, 34, 35 +; CHECK-NEXT: blr + %res = sub <8 x i16> %a, %b + ret <8 x i16> %res +} + +define <4 x i32> @test_xvmuluwm(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_xvmuluwm: +; CHECK: # %bb.0: +; CHECK-NEXT: xvmuluwm 34, 34, 35 +; CHECK-NEXT: blr + %res = mul <4 x i32> %a, %b + ret <4 x i32> %res +} + +define <8 x i16> @test_xvmuluhm(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_xvmuluhm: +; CHECK: # %bb.0: +; CHECK-NEXT: xvmuluhm 34, 34, 35 +; CHECK-NEXT: blr + %res = mul <8 x i16> %a, %b + ret <8 x i16> %res +} + +declare <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32>, <4 x i32>) +define <4 x i32> @test_xvmulhsw(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_xvmulhsw: +; CHECK: # %bb.0: +; CHECK-NEXT: xvmulhsw 34, 34, 35 +; CHECK-NEXT: blr + %res = call <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +declare <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32>, <4 x i32>) +define <4 x i32> @test_xvmulhuw(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_xvmulhuw: +; CHECK: # %bb.0: +; CHECK-NEXT: xvmulhuw 34, 34, 35 +; CHECK-NEXT: blr + %res = call <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +declare <8 x i16> @llvm.ppc.altivec.vmulhsh(<8 x i16>, <8 x i16>) +define <8 x i16> @test_xvmulhsh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_xvmulhsh: +; CHECK: # %bb.0: +; CHECK-NEXT: xvmulhsh 34, 34, 35 +; CHECK-NEXT: blr + %res = call <8 x i16> @llvm.ppc.altivec.vmulhsh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +declare <8 x i16> @llvm.ppc.altivec.vmulhuh(<8 x i16>, <8 x i16>) +define <8 x i16> @test_xvmulhuh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_xvmulhuh: +; CHECK: # %bb.0: +; CHECK-NEXT: xvmulhuh 34, 34, 35 +; CHECK-NEXT: blr + %res = call <8 x i16> @llvm.ppc.altivec.vmulhuh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} diff --git a/llvm/test/CodeGen/PowerPC/pqc-acceleration.ll b/llvm/test/CodeGen/PowerPC/pqc-acceleration.ll deleted file mode 100644 index 176e9785c1cad..0000000000000 --- a/llvm/test/CodeGen/PowerPC/pqc-acceleration.ll +++ /dev/null @@ -1,151 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -mcpu=future < %s | FileCheck %s --check-prefix=CHECK-LE -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -mcpu=future < %s | FileCheck %s --check-prefix=CHECK-BE - -; Test Post Quantum Cryptography Acceleration instructions - -define <4 x i32> @test_xvadduwm(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LE-LABEL: test_xvadduwm: -; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: xvadduwm 34, 34, 35 -; CHECK-LE-NEXT: blr -; -; CHECK-BE-LABEL: test_xvadduwm: -; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: xvadduwm 34, 34, 35 -; CHECK-BE-NEXT: blr - %res = add <4 x i32> %a, %b - ret <4 x i32> %res -} - -define <8 x i16> @test_xvadduhm(<8 x i16> %a, <8 x i16> %b) { -; CHECK-LE-LABEL: test_xvadduhm: -; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: xvadduhm 34, 34, 35 -; CHECK-LE-NEXT: blr -; -; CHECK-BE-LABEL: test_xvadduhm: -; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: xvadduhm 34, 34, 35 -; CHECK-BE-NEXT: blr - %res = add <8 x i16> %a, %b - ret <8 x i16> %res -} - -define <4 x i32> @test_xvsubuwm(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LE-LABEL: test_xvsubuwm: -; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: xvsubuwm 34, 34, 35 -; CHECK-LE-NEXT: blr -; -; CHECK-BE-LABEL: test_xvsubuwm: -; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: xvsubuwm 34, 34, 35 -; CHECK-BE-NEXT: blr - %res = sub <4 x i32> %a, %b - ret <4 x i32> %res -} - -define <8 x i16> @test_xvsubuhm(<8 x i16> %a, <8 x i16> %b) { -; CHECK-LE-LABEL: test_xvsubuhm: -; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: xvsubuhm 34, 34, 35 -; CHECK-LE-NEXT: blr -; -; CHECK-BE-LABEL: test_xvsubuhm: -; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: xvsubuhm 34, 34, 35 -; CHECK-BE-NEXT: blr - %res = sub <8 x i16> %a, %b - ret <8 x i16> %res -} - -define <4 x i32> @test_xvmuluwm(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LE-LABEL: test_xvmuluwm: -; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: xvmuluwm 34, 34, 35 -; CHECK-LE-NEXT: blr -; -; CHECK-BE-LABEL: test_xvmuluwm: -; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: xvmuluwm 34, 34, 35 -; CHECK-BE-NEXT: blr - %res = mul <4 x i32> %a, %b - ret <4 x i32> %res -} - -define <8 x i16> @test_xvmuluhm(<8 x i16> %a, <8 x i16> %b) { -; CHECK-LE-LABEL: test_xvmuluhm: -; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: xvmuluhm 34, 34, 35 -; CHECK-LE-NEXT: blr -; -; CHECK-BE-LABEL: test_xvmuluhm: -; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: xvmuluhm 34, 34, 35 -; CHECK-BE-NEXT: blr - %res = mul <8 x i16> %a, %b - ret <8 x i16> %res -} - -declare <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32>, <4 x i32>) -define <4 x i32> @test_xvmulhsw(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LE-LABEL: test_xvmulhsw: -; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: xvmulhsw 34, 34, 35 -; CHECK-LE-NEXT: blr -; -; CHECK-BE-LABEL: test_xvmulhsw: -; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: xvmulhsw 34, 34, 35 -; CHECK-BE-NEXT: blr - %res = call <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32> %a, <4 x i32> %b) - ret <4 x i32> %res -} - -declare <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32>, <4 x i32>) -define <4 x i32> @test_xvmulhuw(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LE-LABEL: test_xvmulhuw: -; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: xvmulhuw 34, 34, 35 -; CHECK-LE-NEXT: blr -; -; CHECK-BE-LABEL: test_xvmulhuw: -; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: xvmulhuw 34, 34, 35 -; CHECK-BE-NEXT: blr - %res = call <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32> %a, <4 x i32> %b) - ret <4 x i32> %res -} - -declare <8 x i16> @llvm.ppc.altivec.vmulhsh(<8 x i16>, <8 x i16>) -define <8 x i16> @test_xvmulhsh(<8 x i16> %a, <8 x i16> %b) { -; CHECK-LE-LABEL: test_xvmulhsh: -; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: xvmulhsh 34, 34, 35 -; CHECK-LE-NEXT: blr -; -; CHECK-BE-LABEL: test_xvmulhsh: -; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: xvmulhsh 34, 34, 35 -; CHECK-BE-NEXT: blr - %res = call <8 x i16> @llvm.ppc.altivec.vmulhsh(<8 x i16> %a, <8 x i16> %b) - ret <8 x i16> %res -} - -declare <8 x i16> @llvm.ppc.altivec.vmulhuh(<8 x i16>, <8 x i16>) -define <8 x i16> @test_xvmulhuh(<8 x i16> %a, <8 x i16> %b) { -; CHECK-LE-LABEL: test_xvmulhuh: -; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: xvmulhuh 34, 34, 35 -; CHECK-LE-NEXT: blr -; -; CHECK-BE-LABEL: test_xvmulhuh: -; CHECK-BE: # %bb.0: -; CHECK-BE-NEXT: xvmulhuh 34, 34, 35 -; CHECK-BE-NEXT: blr - %res = call <8 x i16> @llvm.ppc.altivec.vmulhuh(<8 x i16> %a, <8 x i16> %b) - ret <8 x i16> %res -} >From d71d6ea22966025614debece71e386d0503a3dc0 Mon Sep 17 00:00:00 2001 From: Lei Huang <[email protected]> Date: Wed, 4 Mar 2026 20:21:45 -0500 Subject: [PATCH 4/5] fix clang-format --- clang/lib/Headers/altivec.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h index 15c5c2d1962b6..ee43a55b7376e 100644 --- a/clang/lib/Headers/altivec.h +++ b/clang/lib/Headers/altivec.h @@ -6405,8 +6405,8 @@ vec_mulh(vector unsigned long long __a, vector unsigned long long __b) { #endif #ifdef __FUTURE_VECTOR__ -static __inline__ vector signed short __ATTRS_o_ai -vec_mulh(vector signed short __a, vector signed short __b) { +static __inline__ vector signed short + __ATTRS_o_ai vec_mulh(vector signed short __a, vector signed short __b) { return __builtin_altivec_vmulhsh(__a, __b); } >From e0cbb8f3be35ed0d40a46567c3d81d5165a9556a Mon Sep 17 00:00:00 2001 From: Lei Huang <[email protected]> Date: Thu, 5 Mar 2026 10:48:40 -0500 Subject: [PATCH 5/5] add pattern to deal with negate vsx vector --- llvm/lib/Target/PowerPC/PPCInstrFuture.td | 55 +++++++++++------------ 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index 18b5b523d2919..47d435f2d1232 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -599,35 +599,34 @@ def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp, let Predicates = [HasVSX, IsISAFuture] in { def : Pat<(v4i32 (rotl v4i32:$vA, v4i32:$vB)), (v4i32 (XVRLW v4i32:$vA, v4i32:$vB))>; +} - // Post Quantum Cryptography Acceleration patterns - // Use AddedComplexity to prefer these patterns over AltiVec patterns - let AddedComplexity = 400 in { - // Vector add - def : Pat<(v4i32 (add v4i32:$XA, v4i32:$XB)), (v4i32 (XVADDUWM $XA, $XB))>; - def : Pat<(v8i16 (add v8i16:$XA, v8i16:$XB)), - (COPY_TO_REGCLASS (XVADDUHM RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; - - // Vector subtract - def : Pat<(v4i32 (sub v4i32:$XA, v4i32:$XB)), (v4i32 (XVSUBUWM $XA, $XB))>; - def : Pat<(v8i16 (sub v8i16:$XA, v8i16:$XB)), - (COPY_TO_REGCLASS (XVSUBUHM RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; - - // Vector multiply - def : Pat<(v4i32 (mul v4i32:$XA, v4i32:$XB)), (v4i32 (XVMULUWM $XA, $XB))>; - def : Pat<(v8i16 (mul v8i16:$XA, v8i16:$XB)), - (COPY_TO_REGCLASS (XVMULUHM RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; - - // Vector multiply high intrinsics - def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$XA, v4i32:$XB)), - (v4i32 (XVMULHSW $XA, $XB))>; - def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$XA, v4i32:$XB)), - (v4i32 (XVMULHUW $XA, $XB))>; - def : Pat<(v8i16 (int_ppc_altivec_vmulhsh v8i16:$XA, v8i16:$XB)), - (COPY_TO_REGCLASS (XVMULHSH RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; - def : Pat<(v8i16 (int_ppc_altivec_vmulhuh v8i16:$XA, v8i16:$XB)), - (COPY_TO_REGCLASS (XVMULHUH RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; - } +// Post Quantum Cryptography Acceleration patterns +// Use AddedComplexity to prefer these patterns over AltiVec patterns +let Predicates = [HasVSX, IsISAFuture], AddedComplexity = 400 in { + // Vector add + def : Pat<(v4i32 (add v4i32:$XA, v4i32:$XB)), (v4i32 (XVADDUWM $XA, $XB))>; + def : Pat<(v8i16 (add v8i16:$XA, v8i16:$XB)), + (COPY_TO_REGCLASS (XVADDUHM RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; + // Vector subtract + // Don't have a VSX negate instruction so use VNEGW instead. + def : Pat<(v4i32 (sub (v4i32 immAllZerosV), v4i32:$vB)), (v4i32 (VNEGW $vB))>; + def : Pat<(v4i32 (sub v4i32:$XA, v4i32:$XB)), (v4i32 (XVSUBUWM $XA, $XB))>; + def : Pat<(v8i16 (sub v8i16:$XA, v8i16:$XB)), + (COPY_TO_REGCLASS (XVSUBUHM RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; + // Vector multiply + def : Pat<(v4i32 (mul v4i32:$XA, v4i32:$XB)), (v4i32 (XVMULUWM $XA, $XB))>; + def : Pat<(v8i16 (mul v8i16:$XA, v8i16:$XB)), + (COPY_TO_REGCLASS (XVMULUHM RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; + // Vector multiply high intrinsics + def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$XA, v4i32:$XB)), + (v4i32 (XVMULHSW $XA, $XB))>; + def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$XA, v4i32:$XB)), + (v4i32 (XVMULHUW $XA, $XB))>; + def : Pat<(v8i16 (int_ppc_altivec_vmulhsh v8i16:$XA, v8i16:$XB)), + (COPY_TO_REGCLASS (XVMULHSH RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; + def : Pat<(v8i16 (int_ppc_altivec_vmulhuh v8i16:$XA, v8i16:$XB)), + (COPY_TO_REGCLASS (XVMULHUH RCCp.AToVSRC, RCCp.BToVSRC), VSRC)>; } //---------------------------- Instruction aliases ---------------------------// _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
