https://github.com/quic-akaryaki updated https://github.com/llvm/llvm-project/pull/184427
>From 4e1a9d5813774133a4bc01597ca4b94e8d26034a Mon Sep 17 00:00:00 2001 From: Alexey Karyakin <[email protected]> Date: Tue, 3 Mar 2026 11:33:02 -0800 Subject: [PATCH] [Hexagon] Ignore formatting of generated proto files hexagon_protos.h, hexagon_circ_brev_intrinsics.h, and hvx_hexagon_protos.h are generated C header files that consist of macro definitions and help fields in comments. These files are large. Automatic formatting of these files breaks their regular structure and increases maintenance effort. --- clang/lib/Headers/.clang-format-ignore | 4 + clang/lib/Headers/hvx_hexagon_protos.h | 182 ++++++++++++++----------- 2 files changed, 106 insertions(+), 80 deletions(-) create mode 100644 clang/lib/Headers/.clang-format-ignore diff --git a/clang/lib/Headers/.clang-format-ignore b/clang/lib/Headers/.clang-format-ignore new file mode 100644 index 0000000000000..5863de2c1d97d --- /dev/null +++ b/clang/lib/Headers/.clang-format-ignore @@ -0,0 +1,4 @@ +# Autogenerated Hexagon intrinsic macros. +hexagon_circ_brev_intrinsics.h +hexagon_protos.h +hvx_hexagon_protos.h diff --git a/clang/lib/Headers/hvx_hexagon_protos.h b/clang/lib/Headers/hvx_hexagon_protos.h index 19309a40d6dd1..9fc0691f7d429 100644 --- a/clang/lib/Headers/hvx_hexagon_protos.h +++ b/clang/lib/Headers/hvx_hexagon_protos.h @@ -5181,8 +5181,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Vdd32.sf=vadd(Vu32.bf,Vv32.bf) - C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Wsf_vadd_VbfVbf(Vu, Vv) \ @@ -5240,8 +5241,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Vd32.bf=vcvt(Vu32.sf,Vv32.sf) - C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Vbf_vcvt_VsfVsf(Vu, Vv) \ @@ -5251,8 +5253,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Qd4=vcmp.gt(Vu32.bf,Vv32.bf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_gt_VbfVbf(Vu, Vv) \ @@ -5263,9 +5266,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Qx4&=vcmp.gt(Vu32.bf,Vv32.bf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred - Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution - Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_gtand_QVbfVbf(Qx, Vu, Vv) \ @@ -5279,9 +5282,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Qx4|=vcmp.gt(Vu32.bf,Vv32.bf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred - Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution - Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_gtor_QVbfVbf(Qx, Vu, Vv) \ @@ -5295,9 +5298,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Qx4^=vcmp.gt(Vu32.bf,Vv32.bf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred - Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution - Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_gtxacc_QVbfVbf(Qx, Vu, Vv) \ @@ -5311,8 +5314,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Vd32.bf=vmax(Vu32.bf,Vv32.bf) - C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Vbf_vmax_VbfVbf(Vu, Vv) \ @@ -5322,8 +5326,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Vd32.bf=vmin(Vu32.bf,Vv32.bf) - C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Vbf_vmin_VbfVbf(Vu, Vv) \ @@ -5333,8 +5338,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Vdd32.sf=vmpy(Vu32.bf,Vv32.bf) - C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Wsf_vmpy_VbfVbf(Vu, Vv) \ @@ -5344,9 +5350,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf) - C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair - Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution - Slots: SLOT23 + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Wsf_vmpyacc_WsfVbfVbf(Vxx, Vu, Vv) \ @@ -5356,8 +5362,9 @@ #if __HVX_ARCH__ >= 73 /* ========================================================================== Assembly Syntax: Vdd32.sf=vsub(Vu32.bf,Vv32.bf) - C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Wsf_vsub_VbfVbf(Vu, Vv) \ @@ -5379,9 +5386,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vx32|=vgetqfext(Vu32.x,Rt32) - C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx, - HVX_Vector Vu, Word32 Rt) Instruction Type: CVI_VX Execution Slots: - SLOT23 + C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 ========================================================================== */ #define Q6_V_vgetqfextor_VVR(Vx, Vu, Rt) \ @@ -5414,8 +5421,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vdd32.hf=vadd(Vu32.f8,Vv32.f8) - C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Whf_vadd_VV(Vu, Vv) \ @@ -5425,8 +5433,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vd32.b=vcvt2(Vu32.hf,Vv32.hf) - C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Vb_vcvt2_VhfVhf(Vu, Vv) \ @@ -5460,8 +5469,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vd32.ub=vcvt2(Vu32.hf,Vv32.hf) - C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Vub_vcvt2_VhfVhf(Vu, Vv) \ @@ -5471,8 +5481,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vd32.f8=vcvt(Vu32.hf,Vv32.hf) - C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector - Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 ========================================================================== */ #define Q6_V_vcvt_VhfVhf(Vu, Vv) \ @@ -5530,8 +5541,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vd32=vmerge(Vu32.x,Vv32.w) - C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector - Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_V_vmerge_VVw(Vu, Vv) \ @@ -5541,8 +5553,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vdd32.hf=vmpy(Vu32.f8,Vv32.f8) - C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Whf_vmpy_VV(Vu, Vv) \ @@ -5552,9 +5565,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vxx32.hf+=vmpy(Vu32.f8,Vv32.f8) - C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair - Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution - Slots: SLOT23 + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Whf_vmpyacc_WhfVV(Vxx, Vu, Vv) \ @@ -5564,8 +5577,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Rt32.hf) - C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32 - Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Vqf16_vmpy_VhfRhf(Vu, Rt) \ @@ -5575,8 +5589,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Rt32.hf) - C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu, - Word32 Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Vqf16_vmpy_Vqf16Rhf(Vu, Rt) \ @@ -5586,8 +5601,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Rt32.sf) - C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32 - Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Vqf32_vmpy_VsfRsf(Vu, Rt) \ @@ -5597,8 +5613,9 @@ #if __HVX_ARCH__ >= 79 /* ========================================================================== Assembly Syntax: Vdd32.hf=vsub(Vu32.f8,Vv32.f8) - C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 ========================================================================== */ #define Q6_Whf_vsub_VV(Vu, Vv) \ @@ -5656,8 +5673,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8) - C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector - Vv, Word32 Rt) Instruction Type: CVI_VA Execution Slots: SLOT0123 + C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_V_valign4_VVR(Vu, Vv, Rt) \ @@ -5763,8 +5781,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv) \ @@ -5775,9 +5794,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred - Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution - Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv) \ @@ -5791,9 +5810,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Qx4|=vcmp.eq(Vu32.hf,Vv32.hf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred - Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution - Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv) \ @@ -5807,9 +5826,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred - Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution - Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv) \ @@ -5823,8 +5842,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv) \ @@ -5835,9 +5855,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred - Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution - Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv) \ @@ -5851,9 +5871,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Qx4|=vcmp.eq(Vu32.sf,Vv32.sf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred - Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution - Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv) \ @@ -5867,9 +5887,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf) - C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred - Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution - Slots: SLOT0123 + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv) \ @@ -5979,8 +5999,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16) - C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv) \ @@ -5990,8 +6011,9 @@ #if __HVX_ARCH__ >= 81 /* ========================================================================== Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32) - C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu, - HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 ========================================================================== */ #define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv) \ _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
