pawosm-arm wrote:
> We'll definitely need some special handling for splats, surely this is
> handled in LLVM-IR correctly?
The printed results are correct, but the IR is kinda horrible. For this
function:
```
int main()
{
cpp::simd<int, cpp::scalable_size<1>> svInt1 = cpp::splat<int,
cpp::scalable_size<1>>(5);
return __builtin_reduce_add(svInt1);
}
```
We can see an explicit `for` loop emitted:
```
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
memory(none) uwtable vscale_range(1,16)
define dso_local noundef i32 @main() local_unnamed_addr #3 {
entry:
%0 = tail call i64 @llvm.vscale.i64()
%1 = shl nuw nsw i64 %0, 2
br label %for.body.i
for.body.i: ; preds = %for.body.i, %entry
%indvars.iv.i = phi i64 [ 0, %entry ], [ %indvars.iv.next.i.3, %for.body.i ]
%sv.04.i = phi <vscale x 4 x i32> [ undef, %entry ], [ %vecins.i.3,
%for.body.i ]
%2 = trunc nuw nsw i64 %indvars.iv.i to i32
%vecins.i = insertelement <vscale x 4 x i32> %sv.04.i, i32 5, i32 %2
%3 = trunc i64 %indvars.iv.i to i32
%4 = or disjoint i32 %3, 1
%vecins.i.1 = insertelement <vscale x 4 x i32> %vecins.i, i32 5, i32 %4
%5 = trunc i64 %indvars.iv.i to i32
%6 = or disjoint i32 %5, 2
%vecins.i.2 = insertelement <vscale x 4 x i32> %vecins.i.1, i32 5, i32 %6
%7 = trunc i64 %indvars.iv.i to i32
%8 = or disjoint i32 %7, 3
%vecins.i.3 = insertelement <vscale x 4 x i32> %vecins.i.2, i32 5, i32 %8
%indvars.iv.next.i.3 = add nuw nsw i64 %indvars.iv.i, 4
%exitcond.not.i.3 = icmp eq i64 %indvars.iv.next.i.3, %1
br i1 %exitcond.not.i.3, label
%_ZN3cppL5splatIiTnDaLin1ETnNS_9enable_ifIX18is_scalable_size_vIXT0_EEEbE4typeELb0EEEDvT0__T_S4_.exit,
label %for.body.i, !llvm.loop !10
_ZN3cppL5splatIiTnDaLin1ETnNS_9enable_ifIX18is_scalable_size_vIXT0_EEEbE4typeELb0EEEDvT0__T_S4_.exit:
; preds = %for.body.i
%rdx.add = tail call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>
%vecins.i.3)
ret i32 %rdx.add
}
```
https://github.com/llvm/llvm-project/pull/183307
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