frno7 wrote:
> ```c
> int test_reorder(int n) {
> asm volatile (
> "1:\n"
> " bnez %0, 1b\n"
> " addiu %0, %0, -1\n"
> : "+r"(n)
> );
> return n;
> }
> ```
>
> Is compiled into this _infinite loop_ without warning:
>
> ```
> .Ltmp0:
> .set noreorder
> bnez $4, .Ltmp0
> nop
> .set reorder
> addiu $4, $4, -1
> ```
>
> Adding `noreorder` to the assembly will produce the expected result, but at
> the same time trigger the short loop bug on the r5900.
Yeah, Maciej might explain this a bit better, but I think the delay slot isn’t
used in canonical MIPS assembly. So unless you have the `noreorder` directive,
your (first) example as it stands is indeed an infinite loop because the ADDIU
is outside the loop... Later revisions of the MIPS ISA removed the delay slot
in hardware too, if memory serves me, as it can be considered an architectural
mistake.
> So like you said:
>
> > they who wield the `noreorder` directive “know what they are doing”
>
> For now I'll consider adding the warning a separate feature out of scope for
> this PR.
Yeah, it’s definitely very nice to have, in my opinion, but not a requirement.
I hope I have made a strong case for its eventual inclusion. :-) Thanks for the
experiments!
https://github.com/llvm/llvm-project/pull/176666
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