Author: Philipp Tomsich Date: 2026-01-12T09:52:23+01:00 New Revision: 43138d627290271b7decd5daf0b5ec23a4171b8d
URL: https://github.com/llvm/llvm-project/commit/43138d627290271b7decd5daf0b5ec23a4171b8d DIFF: https://github.com/llvm/llvm-project/commit/43138d627290271b7decd5daf0b5ec23a4171b8d.diff LOG: [Aarch64] Add support for Ampere1C core (#175442) This patch adds initial support for the ARMv9.2+ Ampere1C core. Added: clang/test/Driver/print-enabled-extensions/aarch64-ampere1c.c Modified: clang/docs/ReleaseNotes.rst clang/test/Driver/aarch64-mcpu.c clang/test/Misc/target-invalid-cpu-note/aarch64.c llvm/docs/ReleaseNotes.md llvm/lib/Target/AArch64/AArch64Processors.td llvm/lib/Target/AArch64/AArch64Subtarget.cpp llvm/lib/TargetParser/Host.cpp llvm/test/CodeGen/AArch64/cpus.ll llvm/unittests/TargetParser/Host.cpp llvm/unittests/TargetParser/TargetParserTest.cpp Removed: ################################################################################ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index f62298938af93..a695d9f0ad4b7 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -701,6 +701,7 @@ X86 Support Arm and AArch64 Support ^^^^^^^^^^^^^^^^^^^^^^^ - Support has been added for the following processors (command-line identifiers in parentheses): + - Ampere Computing Ampere1C (``ampere1c``) - Arm C1-Nano (``c1-nano``) - Arm C1-Pro (``c1-pro``) - Arm C1-Premium (``c1-premium``) diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c index fdf2e4011487a..be5415b735d12 100644 --- a/clang/test/Driver/aarch64-mcpu.c +++ b/clang/test/Driver/aarch64-mcpu.c @@ -102,6 +102,9 @@ // RUN: %clang --target=aarch64 -mcpu=grace -### -c %s 2>&1 | FileCheck -check-prefix=GRACE %s // GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "grace" +// RUN: %clang --target=aarch64 -mcpu=ampere1c -### -c %s 2>&1 | FileCheck -check-prefix=AMPERE1C %s +// AMPERE1C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "ampere1c" + // ================== Check whether -mcpu and -mtune accept mixed-case values. // RUN: %clang --target=aarch64 -mcpu=Cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=CASE-INSENSITIVE-CA53 %s // RUN: %clang --target=aarch64 -mtune=Cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=CASE-INSENSITIVE-CA53-TUNE %s diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1c.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1c.c new file mode 100644 index 0000000000000..d3c1e7ebefd9e --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1c.c @@ -0,0 +1,70 @@ +// REQUIRES: aarch64-registered-target +// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=ampere1c | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s + +// CHECK: Extensions enabled for the given AArch64 target +// CHECK-EMPTY: +// CHECK-NEXT: Architecture Feature(s) Description +// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support +// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension +// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support +// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions +// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension +// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification +// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets +// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions +// CHECK-NEXT: FEAT_CSSC Enable Common Short Sequence Compression (CSSC) instructions +// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction +// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions +// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence +// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence +// CHECK-NEXT: FEAT_DotProd Enable dot product support +// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension +// CHECK-NEXT: FEAT_FAMINMAX Enable FAMIN and FAMAX instructions +// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support +// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension +// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions +// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions +// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing +// CHECK-NEXT: FEAT_FP8 Enable FP8 instructions +// CHECK-NEXT: FEAT_FP8FMA Enable Armv9.5-A FP8 multiply-add instructions +// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int +// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions +// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons +// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register +// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension +// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions +// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension +// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension +// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets +// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions +// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules +// CHECK-NEXT: FEAT_LUT Enable Lookup Table instructions +// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension +// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension +// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement +// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension +// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants +// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension +// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension +// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions +// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions +// CHECK-NEXT: FEAT_RNG Enable Random Number generation instructions +// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier +// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension +// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support +// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support +// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support +// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions +// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit +// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions +// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions +// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions +// CHECK-NEXT: FEAT_SVE_B16B16 Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions +// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions +// CHECK-NEXT: FEAT_SVE_SM4 Enable SVE SM4 instructions +// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions +// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension +// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState +// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension +// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction +// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction diff --git a/clang/test/Misc/target-invalid-cpu-note/aarch64.c b/clang/test/Misc/target-invalid-cpu-note/aarch64.c index a53f23e96842a..3a6cb9d4445eb 100644 --- a/clang/test/Misc/target-invalid-cpu-note/aarch64.c +++ b/clang/test/Misc/target-invalid-cpu-note/aarch64.c @@ -11,6 +11,7 @@ // CHECK-SAME: {{^}}, ampere1 // CHECK-SAME: {{^}}, ampere1a // CHECK-SAME: {{^}}, ampere1b +// CHECK-SAME: {{^}}, ampere1c // CHECK-SAME: {{^}}, apple-a10 // CHECK-SAME: {{^}}, apple-a11 // CHECK-SAME: {{^}}, apple-a12 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 7872e1a9ee551..837037bc387f4 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -117,6 +117,8 @@ Changes to the AArch64 Backend * Added support for C1-Nano, C1-Pro, C1-Premium, and C1-Ultra CPUs. +* Added support for Ampere1C cores. + Changes to the AMDGPU Backend ----------------------------- diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 0fff083ee9db9..af0813e43a960 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -869,6 +869,22 @@ def TuneAmpere1B : SubtargetFeature<"ampere1b", "ARMProcFamily", "Ampere1B", FeatureStpAlignedOnly, FeatureMaxInterleaveFactor4]>; +def TuneAmpere1C : SubtargetFeature<"ampere1c", "ARMProcFamily", "Ampere1C", + "Ampere Computing Ampere-1C processors", [ + FeaturePostRAScheduler, + FeatureFuseAES, + FeatureFuseAdrpAdd, + FeatureALULSLFast, + FeatureAggressiveFMA, + FeatureArithmeticBccFusion, + FeatureCmpBccFusion, + FeatureFuseAddress, + FeatureFuseLiterals, + FeatureStorePairSuppress, + FeatureEnableSelectOptimize, + FeaturePredictableSelectIsExpensive, + FeatureMaxInterleaveFactor4]>; + def TuneOryon : SubtargetFeature<"oryon-1", "ARMProcFamily", "Oryon", "Nuvia Inc Oryon processors", [ @@ -1348,6 +1364,12 @@ def ProcessorFeatures { FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureCCIDX, FeatureRDM]; + list<SubtargetFeature> Ampere1C = [HasV9_2aOps, FeatureNEON, FeatureCSSC, FeatureCCIDX, + FeatureFP8FMA, FeatureFAMINMAX, FeatureLUT, + FeatureSVEAES, FeatureSVESM4, FeatureSVESHA3, + FeatureSVE2, FeatureSVEB16B16, FeatureMTE, + FeatureFP16FML, FeatureSSBS, FeatureRandGen, + FeaturePerfMon]; list<SubtargetFeature> Oryon = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, FeatureRandGen, FeaturePAuth, FeatureSM4, FeatureSHA2, @@ -1586,6 +1608,9 @@ def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A, def : ProcessorModel<"ampere1b", Ampere1BModel, ProcessorFeatures.Ampere1B, [TuneAmpere1B]>; +def : ProcessorModel<"ampere1c", NeoverseN3Model, ProcessorFeatures.Ampere1C, + [TuneAmpere1C]>; + // Qualcomm Oryon def : ProcessorModel<"oryon-1", OryonModel, ProcessorFeatures.Oryon, [TuneOryon]>; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index f3640239809dd..92a7412e83fac 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -322,6 +322,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) { case Ampere1: case Ampere1A: case Ampere1B: + case Ampere1C: CacheLineSize = 64; PrefFunctionAlignment = Align(64); PrefLoopAlignment = Align(64); diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index e9751bdd6fbe6..f545bbfad22b0 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -389,6 +389,7 @@ getHostCPUNameForARMFromComponents(StringRef Implementer, StringRef Hardware, .Case("0xac3", "ampere1") .Case("0xac4", "ampere1a") .Case("0xac5", "ampere1b") + .Case("0xac7", "ampere1c") .Default("generic"); } diff --git a/llvm/test/CodeGen/AArch64/cpus.ll b/llvm/test/CodeGen/AArch64/cpus.ll index fcb727150f68a..f76a2c462c321 100644 --- a/llvm/test/CodeGen/AArch64/cpus.ll +++ b/llvm/test/CodeGen/AArch64/cpus.ll @@ -42,6 +42,7 @@ ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1a 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1b 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1c 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=oryon-1 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID diff --git a/llvm/unittests/TargetParser/Host.cpp b/llvm/unittests/TargetParser/Host.cpp index db88f4fa95f52..bc1af8ae5ff54 100644 --- a/llvm/unittests/TargetParser/Host.cpp +++ b/llvm/unittests/TargetParser/Host.cpp @@ -178,6 +178,9 @@ TEST(getLinuxHostCPUName, AArch64) { EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n" "CPU part : 0xac5"), "ampere1b"); + EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n" + "CPU part : 0xac7"), + "ampere1c"); EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n" "CPU part : 0x001"), "oryon-1"); diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 08f13ab360ac6..b7bd09a73dae0 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1161,6 +1161,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64CPUTestParams("ampere1", "armv8.6-a"), AArch64CPUTestParams("ampere1a", "armv8.6-a"), AArch64CPUTestParams("ampere1b", "armv8.7-a"), + AArch64CPUTestParams("ampere1c", "armv9.2-a"), AArch64CPUTestParams("neoverse-512tvb", "armv8.4-a"), AArch64CPUTestParams("thunderx2t99", "armv8.1-a"), AArch64CPUTestParams("thunderx3t110", "armv8.3-a"), @@ -1270,7 +1271,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64CPUAliasTestParams::PrintToStringParamName); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 97; +static constexpr unsigned NumAArch64CPUArchs = 98; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector<StringRef, NumAArch64CPUArchs> List; _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
