https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/171981
>From 959b7f73fc6a7c542640256927571f767a3a4f68 Mon Sep 17 00:00:00 2001 From: Brandon Wu <[email protected]> Date: Fri, 12 Dec 2025 01:15:38 -0800 Subject: [PATCH 1/2] [AST][RISCV] Preserve RISC-V intrinsic pragma in AST RISC-V vector intrinsic is generated dynamically at runtime, thus it's note preserved in AST yet when using precompile header, neither do information in SemaRISCV. We need to write these information to ast record to be able to use precompile header for RISC-V. Fixes #109634 --- clang/include/clang/Sema/Sema.h | 1 + clang/include/clang/Serialization/ASTBitCodes.h | 3 +++ clang/include/clang/Serialization/ASTReader.h | 3 +++ clang/include/clang/Serialization/ASTWriter.h | 1 + clang/lib/Serialization/ASTReader.cpp | 14 ++++++++++++++ clang/lib/Serialization/ASTWriter.cpp | 11 +++++++++++ clang/test/PCH/riscv-rvv-vectors.c | 14 ++++++++++++++ 7 files changed, 47 insertions(+) create mode 100644 clang/test/PCH/riscv-rvv-vectors.c diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 97b6bb3d1b3a8..9025fa2e0db92 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -66,6 +66,7 @@ #include "clang/Sema/Scope.h" #include "clang/Sema/SemaBase.h" #include "clang/Sema/SemaConcept.h" +#include "clang/Sema/SemaRISCV.h" #include "clang/Sema/TypoCorrection.h" #include "clang/Sema/Weak.h" #include "llvm/ADT/APInt.h" diff --git a/clang/include/clang/Serialization/ASTBitCodes.h b/clang/include/clang/Serialization/ASTBitCodes.h index b48f02c601889..5a86d540e5d0b 100644 --- a/clang/include/clang/Serialization/ASTBitCodes.h +++ b/clang/include/clang/Serialization/ASTBitCodes.h @@ -745,6 +745,9 @@ enum ASTRecordTypes { UPDATE_MODULE_LOCAL_VISIBLE = 76, UPDATE_TU_LOCAL_VISIBLE = 77, + + /// Record code for #pragma clang riscv intrinsic vector. + RISCV_VECTOR_INTRINSICS_PRAGMA = 78, }; /// Record types used within a source manager block. diff --git a/clang/include/clang/Serialization/ASTReader.h b/clang/include/clang/Serialization/ASTReader.h index d276f0d21b958..63f0fde60bb16 100644 --- a/clang/include/clang/Serialization/ASTReader.h +++ b/clang/include/clang/Serialization/ASTReader.h @@ -1079,6 +1079,9 @@ class ASTReader /// The IDs of all decls with function effects to be checked. SmallVector<GlobalDeclID> DeclsWithEffectsToVerify; + /// The RISC-V intrinsic pragma(including RVV, SiFive and Andes). + SmallVector<bool, 3> RISCVVecIntrinsicPragma; + private: struct ImportedSubmodule { serialization::SubmoduleID ID; diff --git a/clang/include/clang/Serialization/ASTWriter.h b/clang/include/clang/Serialization/ASTWriter.h index c77c98dffc39f..634944fa76c19 100644 --- a/clang/include/clang/Serialization/ASTWriter.h +++ b/clang/include/clang/Serialization/ASTWriter.h @@ -640,6 +640,7 @@ class ASTWriter : public ASTDeserializationListener, void WriteDeclsWithEffectsToVerify(Sema &SemaRef); void WriteModuleFileExtension(Sema &SemaRef, ModuleFileExtensionWriter &Writer); + void WriteRISCVIntrinsicPragmas(Sema &SemaRef); unsigned DeclParmVarAbbrev = 0; unsigned DeclContextLexicalAbbrev = 0; diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index aec61322fb8be..bbf14b6e359a0 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -4447,6 +4447,17 @@ llvm::Error ASTReader::ReadASTBlock(ModuleFile &F, for (unsigned I = 0, N = Record.size(); I != N; /*in loop*/) DeclsToCheckForDeferredDiags.insert(ReadDeclID(F, Record, I)); break; + + case RISCV_VECTOR_INTRINSICS_PRAGMA: { + unsigned NumRecords = Record.back(); + // Last record which is used to keep number of valid records. + if (Record.size() - 1 != NumRecords) + return llvm::createStringError(std::errc::illegal_byte_sequence, + "invalid rvv intrinsic pragma record"); + for (unsigned i = 0; i < NumRecords; ++i) + RISCVVecIntrinsicPragma.push_back(Record[i]); + break; + } } } } @@ -9063,6 +9074,9 @@ void ASTReader::UpdateSema() { PointersToMembersPragmaLocation); } SemaObj->CUDA().ForceHostDeviceDepth = ForceHostDeviceDepth; + SemaObj->RISCV().DeclareRVVBuiltins = RISCVVecIntrinsicPragma[0]; + SemaObj->RISCV().DeclareSiFiveVectorBuiltins = RISCVVecIntrinsicPragma[1]; + SemaObj->RISCV().DeclareAndesVectorBuiltins = RISCVVecIntrinsicPragma[2]; if (PragmaAlignPackCurrentValue) { // The bottom of the stack might have a default value. It must be adjusted diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index 667e04049dac8..699e45dc08c06 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -972,6 +972,7 @@ void ASTWriter::WriteBlockInfoBlock() { RECORD(PP_ASSUME_NONNULL_LOC); RECORD(PP_UNSAFE_BUFFER_USAGE); RECORD(VTABLES_TO_EMIT); + RECORD(RISCV_VECTOR_INTRINSICS_PRAGMA); // SourceManager Block. BLOCK(SOURCE_MANAGER_BLOCK); @@ -5232,6 +5233,15 @@ void ASTWriter::WriteModuleFileExtension(Sema &SemaRef, Stream.ExitBlock(); } +void ASTWriter::WriteRISCVIntrinsicPragmas(Sema &SemaRef) { + RecordData Record; + Record.push_back(SemaRef.RISCV().DeclareRVVBuiltins); + Record.push_back(SemaRef.RISCV().DeclareSiFiveVectorBuiltins); + Record.push_back(SemaRef.RISCV().DeclareAndesVectorBuiltins); + Record.push_back(Record.size()); + Stream.EmitRecord(RISCV_VECTOR_INTRINSICS_PRAGMA, Record); +} + //===----------------------------------------------------------------------===// // General Serialization Routines //===----------------------------------------------------------------------===// @@ -6130,6 +6140,7 @@ ASTFileSignature ASTWriter::WriteASTCore(Sema *SemaPtr, StringRef isysroot, WriteFPPragmaOptions(SemaPtr->CurFPFeatureOverrides()); WriteOpenCLExtensions(*SemaPtr); WriteCUDAPragmas(*SemaPtr); + WriteRISCVIntrinsicPragmas(*SemaPtr); } // If we're emitting a module, write out the submodule information. diff --git a/clang/test/PCH/riscv-rvv-vectors.c b/clang/test/PCH/riscv-rvv-vectors.c new file mode 100644 index 0000000000000..30f058753c747 --- /dev/null +++ b/clang/test/PCH/riscv-rvv-vectors.c @@ -0,0 +1,14 @@ +// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +v -emit-pch -o %t %s +// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +v -include-pch %t \ +// RUN: -fsyntax-only -verify %s + +// expected-no-diagnostics + +#ifndef HEADER +#define HEADER +#include <riscv_vector.h> +#else +vuint64m4_t v_add(vuint64m4_t a, vuint64m4_t b, size_t vl) { + return __riscv_vadd_vv_u64m4(a, b, vl); +} +#endif >From c448a53bc0e210959a41a84aa12529f24b8c4fc3 Mon Sep 17 00:00:00 2001 From: Brandon Wu <[email protected]> Date: Fri, 12 Dec 2025 02:00:20 -0800 Subject: [PATCH 2/2] fixup! check empty --- clang/lib/Serialization/ASTReader.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index bbf14b6e359a0..d988b9ec48d9d 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -9074,9 +9074,11 @@ void ASTReader::UpdateSema() { PointersToMembersPragmaLocation); } SemaObj->CUDA().ForceHostDeviceDepth = ForceHostDeviceDepth; - SemaObj->RISCV().DeclareRVVBuiltins = RISCVVecIntrinsicPragma[0]; - SemaObj->RISCV().DeclareSiFiveVectorBuiltins = RISCVVecIntrinsicPragma[1]; - SemaObj->RISCV().DeclareAndesVectorBuiltins = RISCVVecIntrinsicPragma[2]; + if (!RISCVVecIntrinsicPragma.empty()) { + SemaObj->RISCV().DeclareRVVBuiltins = RISCVVecIntrinsicPragma[0]; + SemaObj->RISCV().DeclareSiFiveVectorBuiltins = RISCVVecIntrinsicPragma[1]; + SemaObj->RISCV().DeclareAndesVectorBuiltins = RISCVVecIntrinsicPragma[2]; + } if (PragmaAlignPackCurrentValue) { // The bottom of the stack might have a default value. It must be adjusted _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
