================
@@ -2125,7 +2125,7 @@ def : InstRW<[V2Write_2c_1V],
"^ADR_LSL_ZZZ_[SD]_[0123]",
"^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
"^SADDLBT_ZZZ_[HSD]",
- "^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",
+ "^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]",
----------------
c-rhodes wrote:
slightly unrelated but i noticed V3 doesnt need updating here, I guess because
you just fixed `AArch64SVESchedPseudoTest` and it doesnt cover all cores:
https://github.com/llvm/llvm-project/blob/60492898f8d4143f99f1dc2d3015e97f56acc870/llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp#L105-L124
If we want to keep scheduling info of pseudos inline with real instructions I
wonder if we should stop setting
https://github.com/llvm/llvm-project/blob/60492898f8d4143f99f1dc2d3015e97f56acc870/llvm/lib/Target/AArch64/SVEInstrFormats.td#L803
so we catch this at compile-time
https://github.com/llvm/llvm-project/pull/170894
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