================
@@ -100,6 +100,28 @@ static bool checkWaveOps(Intrinsic::ID IID) {
}
}
+// Checks to see if the status bit from a load with status
+// instruction is ever extracted.
+// This is our proof that the module requires TiledResources
+// to be set, as if check access fully mapped was used.
+bool checkIfStatusIsExtracted(const IntrinsicInst &II) {
+ [[maybe_unused]] Intrinsic::ID IID = II.getIntrinsicID();
+ assert(IID == Intrinsic::dx_resource_load_typedbuffer ||
+ IID == Intrinsic::dx_resource_load_rawbuffer &&
+ "unexpected intrinsic ID, only dx_resource_load_typedbuffer and "
+ "dx_resource_load_rawbuffer are expected");
+ for (const User *U : II.users()) {
+ if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U)) {
+ // Resource load operations return a {result, status} pair
+ // check if we extract the status
----------------
hekota wrote:
```suggestion
// Resource load operations return a {result, status} pair.
// Check if we extract the status.
```
https://github.com/llvm/llvm-project/pull/166449
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