================ @@ -827,6 +827,53 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) ret #endif +// +// extern "C" bool __libunwind_Registers_arm64_za_disable() +// +// On return: +// success (true/false) is returned in x0 +// + .p2align 2 +DEFINE_LIBUNWIND_FUNCTION(__libunwind_Registers_arm64_za_disable) + // If TPIDR2_EL0 is null, the subroutine does nothing. + .inst 0xd53bd0b0 // mrs x16, TPIDR2_EL0 ---------------- sdesmalen-arm wrote:
>From the >[docs](https://developer.arm.com/documentation/ddi0601/2025-09/AArch64-Registers/TPIDR2-EL0--EL0-Read-Write-Software-Thread-ID-Register-2): > This register is present only when FEAT_SME is implemented and FEAT_AA64 is > implemented. Otherwise, direct accesses to TPIDR2_EL0 are UNDEFINED So this function assumes that SME is available, which is fine given how it's used (because it's only called when `_misc_registers.__has_sme` is non-zero). Can you add a comment to the description of the function that this assumption is made and that this function should not be called if SME may not be available? https://github.com/llvm/llvm-project/pull/165451 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
