================
@@ -3780,6 +3751,89 @@ bool
SPIRVInstructionSelector::selectResourceNonUniformIndex(
return true;
}
+bool SPIRVInstructionSelector::selectF16ToF32(Register ResVReg,
+ const SPIRVType *ResType,
+ MachineInstr &I) const {
+ assert(I.getNumOperands() == 3);
+ assert(I.getOperand(0).isReg());
+ assert(I.getOperand(2).isReg());
+ Register SrcReg = I.getOperand(2).getReg();
+ const SPIRVType *SrcRegType = GR.getSPIRVTypeForVReg(SrcReg);
+ LLT SrcType = MRI->getType(SrcReg);
+ SPIRVType *SrcEltType = GR.getScalarOrVectorComponentType(SrcRegType);
+ SPIRVType *ResEltType = GR.getScalarOrVectorComponentType(ResType);
+ const TargetRegisterClass *SrcRegClass = GR.getRegClass(SrcEltType);
+ const TargetRegisterClass *ResRegClass = GR.getRegClass(ResEltType);
+ MachineIRBuilder MIRBuilder(I);
+ const SPIRVType *Vec2ResType =
+ GR.getOrCreateSPIRVVectorType(ResEltType, 2, MIRBuilder, false);
+ const TargetRegisterClass *Vec2RegClass = GR.getRegClass(Vec2ResType);
+
+ bool Result = true;
----------------
s-perron wrote:
If we want to use the capabilities we could do
%1 = OpUConvert %short %input
%2 = OpBitcast %half %1
%3 = OpFConvert %float %2
The same three instructions work if the type is a vector too.
https://github.com/llvm/llvm-project/pull/165860
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