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``````````
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``````````diff
diff --git a/clang/lib/Headers/hvx_hexagon_protos.h
b/clang/lib/Headers/hvx_hexagon_protos.h
index 5896e3b43..19309a40d 100644
--- a/clang/lib/Headers/hvx_hexagon_protos.h
+++ b/clang/lib/Headers/hvx_hexagon_protos.h
@@ -5613,7 +5613,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf16_vabs_Vhf(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu)
+#define Q6_Vqf16_vabs_Vhf(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5624,7 +5625,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf16_vabs_Vqf16(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu)
+#define Q6_Vqf16_vabs_Vqf16(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5635,7 +5637,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf32_vabs_Vqf32(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu)
+#define Q6_Vqf32_vabs_Vqf32(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5646,18 +5649,19 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf32_vabs_Vsf(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu)
+#define Q6_Vqf32_vabs_Vsf(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8)
- C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu,
HVX_Vector Vv, Word32 Rt)
- Instruction Type: CVI_VA
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector
+ Vv, Word32 Rt) Instruction Type: CVI_VA Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_V_valign4_VVR(Vu,Vv,Rt)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu,Vv,Rt)
+#define Q6_V_valign4_VVR(Vu, Vv, Rt)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu, Vv, Rt)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5668,7 +5672,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vbf_equals_Wqf32(Vuu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu)
+#define Q6_Vbf_equals_Wqf32(Vuu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5679,7 +5684,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_V_equals_Vqf16(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu)
+#define Q6_V_equals_Vqf16(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5690,7 +5696,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vh_equals_Vhf_rnd(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu)
+#define Q6_Vh_equals_Vhf_rnd(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5701,7 +5708,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Wqf16_equals_V(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu)
+#define Q6_Wqf16_equals_V(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5712,7 +5720,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf16_equals_Vhf(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu)
+#define Q6_Vqf16_equals_Vhf(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5723,7 +5732,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf16_equals_Vqf16(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu)
+#define Q6_Vqf16_equals_Vqf16(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5734,7 +5744,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf32_equals_Vqf32(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu)
+#define Q6_Vqf32_equals_Vqf32(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5745,95 +5756,128 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf32_equals_Vsf(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu)
+#define Q6_Vqf32_equals_Vsf(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf)
- C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu,
HVX_Vector Vv)
- Instruction Type: CVI_VA
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu,
+ HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Q_vcmp_eq_VhfVhf(Vu,Vv)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu,Vv)),-1)
+#define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(
\
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu, Vv)), -1)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf)
- C Intrinsic Prototype: HVX_VectorPred
Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
- Instruction Type: CVI_VA
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
==========================================================================
*/
-#define Q6_Q_vcmp_eqand_QVhfVhf(Qx,Vu,Vv)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(
\
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)(
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,
\
+ Vv)),
\
+ -1)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.eq(Vu32.hf,Vv32.hf)
- C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred
Qx, HVX_Vector Vu, HVX_Vector Vv)
- Instruction Type: CVI_VA
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
==========================================================================
*/
-#define Q6_Q_vcmp_eqor_QVhfVhf(Qx,Vu,Vv)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(
\
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)(
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,
\
+ Vv)),
\
+ -1)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf)
- C Intrinsic Prototype: HVX_VectorPred
Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
- Instruction Type: CVI_VA
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_VectorPred
Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
==========================================================================
*/
-#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx,Vu,Vv)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(
\
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)(
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,
\
+ Vv)),
\
+ -1)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf)
- C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu,
HVX_Vector Vv)
- Instruction Type: CVI_VA
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu,
+ HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Q_vcmp_eq_VsfVsf(Vu,Vv)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu,Vv)),-1)
+#define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(
\
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu, Vv)), -1)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf)
- C Intrinsic Prototype: HVX_VectorPred
Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
- Instruction Type: CVI_VA
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
==========================================================================
*/
-#define Q6_Q_vcmp_eqand_QVsfVsf(Qx,Vu,Vv)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(
\
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)(
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,
\
+ Vv)),
\
+ -1)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.eq(Vu32.sf,Vv32.sf)
- C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred
Qx, HVX_Vector Vu, HVX_Vector Vv)
- Instruction Type: CVI_VA
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
==========================================================================
*/
-#define Q6_Q_vcmp_eqor_QVsfVsf(Qx,Vu,Vv)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(
\
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)(
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,
\
+ Vv)),
\
+ -1)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf)
- C Intrinsic Prototype: HVX_VectorPred
Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
- Instruction Type: CVI_VA
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_VectorPred
Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
==========================================================================
*/
-#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx,Vu,Vv)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
+#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(
\
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)(
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu,
\
+ Vv)),
\
+ -1)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5844,7 +5888,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vw_vilog2_Vhf(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu)
+#define Q6_Vw_vilog2_Vhf(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5855,7 +5900,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vw_vilog2_Vqf16(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu)
+#define Q6_Vw_vilog2_Vqf16(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5866,7 +5912,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vw_vilog2_Vqf32(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu)
+#define Q6_Vw_vilog2_Vqf32(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5877,7 +5924,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vw_vilog2_Vsf(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu)
+#define Q6_Vw_vilog2_Vsf(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5888,7 +5936,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf16_vneg_Vhf(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu)
+#define Q6_Vqf16_vneg_Vhf(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5899,7 +5948,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf16_vneg_Vqf16(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu)
+#define Q6_Vqf16_vneg_Vqf16(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5910,7 +5960,8 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf32_vneg_Vqf32(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu)
+#define Q6_Vqf32_vneg_Vqf32(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
@@ -5921,29 +5972,30 @@
Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf32_vneg_Vsf(Vu)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu)
+#define Q6_Vqf32_vneg_Vsf(Vu)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16)
- C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu,
HVX_Vector Vv)
- Instruction Type: CVI_VS
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu,
+ HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf16_vsub_VhfVqf16(Vu,Vv)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu,Vv)
+#define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu, Vv)
#endif /* __HEXAGON_ARCH___ >= 81 */
#if __HVX_ARCH__ >= 81
/* ==========================================================================
Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32)
- C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu,
HVX_Vector Vv)
- Instruction Type: CVI_VS
- Execution Slots: SLOT0123
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu,
+ HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123
==========================================================================
*/
-#define Q6_Vqf32_vsub_VsfVqf32(Vu,Vv)
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu,Vv)
+#define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv)
\
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu, Vv)
#endif /* __HEXAGON_ARCH___ >= 81 */
#endif /* __HVX__ */
``````````
</details>
https://github.com/llvm/llvm-project/pull/165903
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